View S1R72801F00A_827418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mf1385 - 04 technical manual S1R72801F00A technical manual ieee1394 controller S1R72801F00A technical manual S1R72801F00A epson electronic devices website electronic devices marketing division http://www.epson.co.jp/device/ first issue december,2000 printed march,2001 in japan h a 4.5mm this manual was made with recycle paper, and printed using soy-based inks.
in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no parts of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export licence from teh ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001, all rights reserved. all other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies.
the information of the product number change starting april 1, 2001 the product number will be changed as listed below. to order from april 1, 2001 please use the new product number. for further information, please contact epson sales representative. configuration of product number l devices s1 r 72801 f 00a1 00 packing specification specifications shape (f:qfp) model number model name (r:exclusive use controller, peripheral) product classification (s1:semiconductors) comparison table between new and previous number previous number new number spc7281f 0a S1R72801F00A e0c33000 s1c33000
spc7281f 0a epson i contents 1. description .................................................................................................................. ................................ 1 2. features ..................................................................................................................... ................................... 1 3. internal block description ................................................................................................... ............... 3 3.1 block diagram ............................................................................................................... ...................... 3 3.2 block diagram description ................................................................................................... ......... 3 4. internal connection diagram .................................................................................................. ............ 4 5. pin assignment diagram ....................................................................................................... ................... 5 6. pin description .............................................................................................................. ............................. 6 7. functional description ....................................................................................................... ................. 10 7.1 memory map .................................................................................................................. ...................... 10 7.1.1 all memory space .......................................................................................................... ................ 10 7.1.2 ieee1394link/transaction controller xcsbuf area (sram) ..................................................... 11 7.2 ieee1394 packet format ...................................................................................................... ........... 12 7.2.1 transmit packet format .................................................................................................... ............ 12 7.2.2 receive packet format ..................................................................................................... ............. 14 7.3 ieee1394 hardware sbp-2 control ............................................................................................. 17 7.4 ide interface control ....................................................................................................... ............ 17 7.5 built-in cpu ................................................................................................................ .......................... 17 7.6 flash controller ............................................................................................................ ................ 18 8. internal register ............................................................................................................ ........................ 19 8.1 ieee1394 link controller register mapping ......................................................................... 19 8.1.1 register table ............................................................................................................ ................... 19 8.1.2 register/bit table ........................................................................................................ .................. 22 8.1.3 register map .............................................................................................................. ................... 26 8.1.4 detail description of register ............................................................................................ ............ 42 8.2 flash rom control register .................................................................................................. .... 88 9. electrical characteristics ................................................................................................... ............. 91 9.1 absolute maximum ratings .................................................................................................... ....... 91 9.2 recommended operating condition ......................................................................................... 91 9.3 dc characteristics (according to recommended operating condition) ................ 92 9.4 ac characteristics .......................................................................................................... ............... 94 9.4.1 clock timing .............................................................................................................. .................... 94 9.4.2 phy-link interface timing ................................................................................................. .......... 95 9.4.3 ide interface timing ...................................................................................................... ................ 96 9.4.4 cpu interface timing ...................................................................................................... ............ 102 10. examples of external connection for reference purposes ........................................... 103 11. shape of package ............................................................................................................ ...................... 106
S1R72801F00A epson 1 1. description the S1R72801F00A is a link/transaction controller based on the ieee std. 1394-1955, p1394a draft 2.0. it integrates a built-in cpu and flash rom, and also integrates a part of transaction functions into hardware. if you set a pagetable address and its size, it can automatically fetch subsequent pagetables and transmit data. it can offer a 1394 interface optimum to computer peripherals in combination with the cable phy transceiver arbiter based on the above standard. 2. features l link/transaction controller link layer ready for all two-way data transfer in asynchronous and isochronous modes. the built-in sram realized stable two-way data transfer up to max. payload of 100mbps, 200mbps, and 400mbps. can automatically detect the isochronous resource manager by hardware. transaction layer integrates a part of transaction functions into hardware to prevent deterioration of actual data transmission rate due to the overhead of firmware (assure a special area). a header area is distinguished from a data area to simplify communications with a higher rank layer. furthermore, it segments a data area to a stream area and orb area. adopts a ring buffer to the receive header area, receive data area (receive stream area, receive orb area) and transmit data area (transmit stream area). can arbitrarily set the size of each area. automatically controls the busy when hardware receives data. l sbp-2 support can set an pagetable address and its size for the sbp-2 to automatically perform subsequent page table fetches and data transfers. l phy/link interface ready for the p1394a. ready for the data transfer rate of 100/200/400mbps. ready for isolation (bus holder integrated) l ide interface ready for the pio mode 0/1/2/3/4, multi-word dma mode 0/1/2, ultra-dma mode 0/1/2. usable as a general port interface as well.
S1R72801F00A 2 epson l built-in cpu integration of a cpu eliminated the necessity of an external cpu to control this ic. cpu core: 32-bit risc cpu s1c33000 harvard architecture (concurrency of a fetch and load/store) high speed/high performance: ready for operation with 50mhz command set: 16-bit fixed length, 105 types of basic commands execution cycle: execution at one cycle/command regarding a main command and/or (mac) operation: 16 bits 16 bits + 64 bits, 2 clocks/ mac (25 mops at 50mhz) cpu register: 16 32-bit general registers and 5 32- bit special registers memory space:linear space where 256-mbyte (28- bit) code, data, and i/o can be mapped. external bus interface: directly connects the external memory of the memory area. programmable wait cycle (7 cycles, max.) enables handshake through the xwait terminal. interrupt: ready for reset, nmi, max. 128 external interrupts, 4 software interrupts, and 2 exceptions reset, boot: cold reset, hot reset built-in ram: 8kbytes l flash rom integration of a flash rom eliminated the necessity of a rom to externally store programs. ? memory structure: memory size 512k (32k 16) bits ? sector size: 512 words/sector ? unit of erase: per chip or sector ? unit of write: writing with words ? erase/write time: chip erase time 100ms (standard) sector erase time 20ms (standard) write time: 15 m s (standard) ? access time: 90nsec. (max.) ? reliability: no. of erase/write 1,000 times data retention: 10 years l others a boot rom (4mbbytes, max.) is connectable to outside of this ic. supply voltage, 5.0v 10% and 3.3v 0.3v 184pinqfp (0.4mm pitch) not radiation resistant. the cpu core built into this ic is an original 32-bit risc cpu from seiko epson. regarding the cpu core, refer to the e0c33208/204/202 technical manual. the built-in ram is 8kbytes. note: in the built-in cpu core, a dma controller and a/d converter are not integrated; this part is different from the description on the dma controller and a/d converter given in technical manual (and macro manual). a low speed oscillation circuit (osc1) is not available.
S1R72801F00A epson 3 fig. 3.1 block diagram 3. internal block description 3.1 block diagram intenal packet memory (8kbyte) buffer i/f maneger ide fifo dma for atf dma for itf dma for rf rx fifo isotx fifo asynctx fifo ide dma register for ide flash rom 64kbyte (32kword x 16bit) internal ram (8kbyte) c33_core (cpu, bcu, itc, clg, dbg) c33_peri (prescaaler, 8-bit timer, 16bit timer, clock timer, serial interface, ports) c33_sbus c33 core block c33 peripheral block c33 macro block ide i/f tran & sbp2 control register for tran&sbp2 register for 1394tx/rx 1394 link & tran core 1394 phy/link i/f d [7:0] ctl [1:0] lreq lps linkon bhen xiso sclk register for link&tran ad [23:0] dt [15:0] xce10_ex xce [9:4] ea10md [1:0] xwait ext_md xrd xwr xwrh bclk p[14:04] srdy sclk sout sin hdd [15:0] hdmarq xhior xhiow xhdmack hiordy hintrq xhpdiag hda [2:0] xcs [1:0] xhdasp xhrst osc4 osc3 plls1 plls0 icemd dsio x2spd xnmi xrest tvep c33 internal memory block core pad peri pad 3.2 block diagram description l c33 core block the c33 core block consists of the function block- c33_core- that includes the cpu, bcu (bus control unit), itc (interrupt controller), clg (clock generator), and dbg (debug unit), the external interface i/o pad block-pad_core, pad_core_option-, and the block to interface with the peripheral circuits on the chip -sbus-. l c33_peri block (c33 peripheral circuit block) the c33_peri block consists of the psc (prescaler), 6-channel t8 (8-bit programmable timer), wdt (watch dog timer), 6-channel t16 with an event counter (16-bit programmable timer), 4-channel sio (serial interface), input and i/o ports, and ctm (clock timer). l internal ram block sram for the built-in memory area (area 0). l internal flash block flash for the built-in memory area (area 10).
S1R72801F00A 4 epson fig. 4.1 internal connection diagram 4. internal connection diagram u_ad<23:0> xreset ad<23:00> dt<15:00> xce10ex xce9 xce8 xce6 xrd xwrl xwrh ea10md2 ea10md1 ea10md0 bclk c33 core xnmi x2spdx icemd dsio osc3 osc4 pllc plls1 plls0 u_dt<15:0> xcsreg xcsbuf xcsfreg lps(p35) pd(p34) cna(k64) k66 k67 p20 p21 p22 p23 xcsfls xwrl xrd xwait xrst xint(k65) sleep(p33) u_ad<12:0> u_dt<7:0> xcsreg xcsbuf xwrl xrd xwait xrst xint sleep u_ad<14:0> u_dt<15:0> xcsfreg xwrl u_ad<14:0> u_dt<15:0> flash rom (64kb) flash controller 1394link core xcs xrd xrd hdd<15:0> hda<2:0> xhcs<1:0> xhrst xhiow bhen monxwait monxint xiso linkon lps lreq ctl<1:0> d<7:0> sclk xhior hdmarq xhdmack hiordy xhpdiag xhdasp hintrq p10 p11 p12 p13 p14 p00 p01 p02 p03 p04 p05 p06 p07
S1R72801F00A epson 5 5. pin assignment diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 lv dd n.c. dt0 dt1 hv dd dt2 dt3 dt4 dt5 dt6 dt7 dt8 v ss dt9 dt10 dt11 dt12 dt13 dt14 dt15 hv dd xwrh xwrl xrd ad0 ad1 ad2 ad3 v ss ad4 ad5 ad6 ad7 ad8 ad9 ad10 hv dd ad11 ad12 ad13 ad14 ad15 ad16 ad17 n.c. v ss 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 v ss n.c. p21 p20 xce10ex xce9 monxwait xce6 hv dd to0 to1 to2 to3 to4 to5 to6 to7 ti8 monxint v ss v ss v ss v ss lreq lv dd sclk v ss cna xiso bhen ctl0 ctl1 d0 d1 d2 lv dd d3 d4 d5 d6 d7 pd lps linkon n.c. lv dd 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 v ss n.c. xhrst hdd7 hdd8 hdd6 hdd9 hdd5 hdd10 hv dd hdd4 hdd11 hdd3 hdd12 hdd2 hdd13 hdd1 v ss hdd14 hdd0 hdd15 hdmarq xhiow xhior hiordy hv dd xhdmack hintrq hda1 xhpdiag hda0 hda2 xhcs0 xhcs1 tvep v ss xhdasp flstst ad23 ad22 ad21 ad20 ad19 ad18 n.c. lv dd 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 lv dd n.c. p22 p23 k66 k67 xwait p00 p01 v ss p02 p03 p04 p05 p06 p07 x2spdx ramtst v ss pllc v ss plls0 plls1 ea10md0 ea10md1 ea10md2 hv dd p14 p13 p12 p11 v ss osc3 osc4 v ss p10 dsio hv dd xnmi xreset icemd v ss hclk bclk n.c. v ss index epson S1R72801F00A top view
S1R72801F00A 6 epson 6. pin description control signals with an x as the first character of a pin name are low active. (excluding x2spd) pin name pin i/o reset pin function remarks 1394phy interface (lv dd ) d7 98 b hi-z (msb) d6 99 b hi-z d5 100 b hi-z try state output d4 101 b hi-z data bus with phy drive ability 12ma d3 102 b hi-z d2 104 b hi-z schmitt input (bus holder) d1 105 b hi-z d0 106 b hi-z (lsb) ctl1 107 b hi-z tray state output ctl0 108 b hi-z drive ability 12ma schmitt input (bus holder) lreq 115 o lo link request signal to phy drive ability 12ma lps 96 o lo link power status signal to phy drive ability 12ma linkon 95 i C link on signal from phy schmitt input (bus holder) xiso 110 i C selects connection to phy cmos input (l: annex-j isolarion) bhen 109 i C bus holder enable signal (h: enable) cmos schmitt input cna 111 i cabele not active pd 97 o power down enable sclk 113 i C clock signal from phy (49.152mhz) schmitt input (bus holder) ide interface (hv dd ) hdd15 72 b hi-z (msb) hdd14 74 b hi-z hdd13 77 b hi-z hdd12 79 b hi-z hdd11 81 b hi-z hdd10 84 b hi-z hdd9 86 b hi-z hdd8 88 b hi-z ide data bus drive ability 3ma hdd7 89 b hi-z hdd6 87 b hi-z hdd5 85 b hi-z hdd4 82 b hi-z hdd3 80 b hi-z hdd2 78 b hi-z hdd1 76 b hi-z hdd0 73 b hi-z (lsb) hdmarq 71 b hi-z ide dma request signal drive ability 6ma xhiow 70 b hi-z ide write signal drive ability 3ma xhior 69 b hi-z ide read signal drive ability 3ma hiordy 68 i C ide iordy signal xhdmack 66 b hi-z ide dma acknowledge signal hintrq 65 i C ide interrupt signal xhpdiag 63 i C ide pdiag signal
S1R72801F00A epson 7 pin name pin i/o reset pin function remarks ide interface (hv dd ) hda2 61 otr hi-z (msb) hda1 64 otr hi-z ide address signal hda0 62 otr hi-z (lsb) xhcs1 59 otr hi-z ide chip select signal xhcs0 60 otr hi-z ide chip select signal xhdasp 56 i C ide dasp signal drive ability 3ma xhrst 90 otr hi-z ide reset signal drive ability 6ma c33 external interface (hv dd ) ad23 54 o lo (msb) ad22 53 o lo ad21 52 o lo ad20 51 o lo ad19 50 o lo ad18 49 o lo ad17 44 o lo ad16 43 o lo ad15 42 o lo cpu address bus ad14 41 o lo ad13 40 o lo ad12 39 o lo ad11 38 o lo ad10 36 o lo ad9 35 o lo ad8 34 o lo ad7 33 o lo ad6 32 o lo ad5 31 o lo ad4 30 o lo ad3 28 o lo ad2 27 o lo ad1 26 o lo ad0 25 o lo (lsb) dt15 20 b hi-z (msb) dt14 19 b hi-z dt13 18 b hi-z dt12 17 b hi-z dt11 16 b hi-z dt10 15 b hi-z dt9 14 b hi-z dt8 12 b hi-z cpu data buss dt7 11 b hi-z dt6 10 b hi-z dt5 9 b hi-z dt4 8 b hi-z dt3 7 b hi-z dt2 6 b hi-z dt1 4 b hi-z dt0 3 b hi-z (lsb)
S1R72801F00A 8 epson pin name pin i/o reset pin function remarks c33 external interface (hv dd ) p07 154 b general i/o port 07 pull up resistor integrated p06 153 b general i/o port 06 pull up resistor integrated p05 152 b general i/o port 05 pull up resistor integrated p04 151 b general i/o port 04 pull up resistor integrated srdy(p03) 150 b serial i/f ready signal input pull up resistor integrated pin-cum-general i/o port 03 sclk(p02) 149 b serial i/f clock input pull up resistor integrated pin-cum-general i/o port 02 sout(p01) 147 b serial i/f data output pull up resistor integrated pin-cum-general i/o port 01 sin(p00) 146 b serial i/f data input pull up resistor integrated pin-cum-general i/o port 00 k67 144 i pull up resistor integrated k66 143 i pull up resistor integrated p23 142 b pull up resistor integrated p22 141 b pull up resistor integrated p21 136 b pull up resistor integrated p20 135 b pull up resistor integrated xce10_ex 134 o hi external memory area 10 chip enable xce9 133 o hi area 9 chip enable xce6 131 o hi area 6 chip enable ea10m2 164 i area 10 boot mode select 2 ea10m1 163 i area 10 boot mode select 1 ea10m0 162 i area 10 boot mode select 0 xwait 145 i wait cycle input xrd 24 o hi read signal xwrh 22 o hi higher order byte write signal xwrl 23 o hi lower order byte write signal bclk 182 o hi bus clock signal c33 external interface (lv dd ) p14 166 b lo general i/o port 14 (for icd) p13 167 b lo general i/o port 13 (for icd) p12 168 b lo general i/o port 12 (for icd) p11 169 b lo general i/o port 11 (for icd) p10 174 b lo general i/o port 10 (for icd) dsio 175 b serial i/o pin for debug: pull up resister integrated use for communication with icd33. clock generator pin osc4 172 o high speed oscillation output osc3 171 i high speed oscillation output (xtal/ceramic oscillation or external clock input) plls1 161 i pll set pin 1 pll circuit is not usable. plls0 160 i pll set pin 0 connect to gnd. pllc 158 C capacitor connection pin for pll non-connect pin
S1R72801F00A epson 9 pin name pin i/o reset pin function remarks other pins icemd 179 i hi-impedance control: set hi-z pull down resistor integrated for all outputs. x2psdx 155 i bus speed mode set pin high : bclk = cpu clock low : bclk = half cpu clock xnmi 177 i nmiinput pin xreset 178 i initial reset hclk 181 o half sclk frequency division output tvep 58 C flash test pin connect to hv dd when it is mounted. test pin ti8 121 i schmitt input (bus holder) to7 122 o C (msb) to6 123 o C to5 124 o C to4 125 o C to3 126 o C to2 127 o C to1 128 o C to0 129 o C (lsb) flstst 55 i C built-in flash test pin pull down resistor integrated ramtst 156 i C built-in sram test pin pull down resistor integrated monxwait 132 o C internal logic xwait monitor pin monxint 120 o C internal logic xint monitor pin power pin hv dd C p high high power (5v) 5,21,37,67,83,130,165,176 (8 pins) lv dd C p low low power (3.3v) 1,47,93,103,114,139 (6 pins) v ss C p gnd 148,157,159,170,173,180,184 13,29,46,57,75,92,112,116,117, 118,119,138 (19 pins) n.c. pin n.c. C C 2,45,48,91,94,137,140,183 (8 pins) table 6.1 settings of ea10m2, ea10m1, and ea10m0 (area 10 boot mode) p_ea10m2 p_ea10m1 p_ea10m0 function 1 1 1 built-in flash boot mode 0 1 1 external rom mode note) other settings are not available on this ic.
S1R72801F00A 10 epson 7. functional description 7.1 memory map 7.1.1 all memory space area address area 0 0x000000 cpu-integrated ram (8kb) 0x002000 (mirror of cpu-integrated ram) area 1 0x030000 (mirror of cpu-integrated peripheral circuit control register) 0x040000 cpu-integrated peripheral circuit control register 0x050000 (mirror of cpu-integrated peripheral circuit control register) area 2 0x060000 reserved area 3 0x080000 reserved area 4 0x100000 ieee1394link/transaction controller x csreg area (control register) 0x100080 reserved area 5 0x200000 flash rom control register 0x200008 reserved area 6 0x300000 reserved area 7 0x400000 ieee1394link/transaction controller xcsbuf area (sram: 8kb) 0x402000 reserved area 8 0x600000 reserved area 9 0x800000 reserved area 10 0xc00000 internal flash rom (64kb) 0xc10000 external rom reserved (4mb) 0xffffff
S1R72801F00A epson 11 ? all ram areas are accessible from the cpu by direct addressing. ? hardware dma is possible to the ide i/f for the rxstreamarea and txstreamarea. ? hw_pagetablearea (the equivalent of 24 pages) and hw_rxheaderarea and hw_txheaderarea (the equivalent of 1 header, respectively) are assured. the rxorb and txorb areas are usable by firmware alone. ? the rxheaderarea, rxorbarea, txorb, txstreamarea and rxstreamarea are ringbuffers. even at the time of execution of data transmission/ reception according to 1394 or ide dma, data among the areas are guaranteed by hardware . (the size of each ringbuffer is variable by settings on the txstreamareastart, txstreamareaend, and rxstreamareastart.) ? the txstreamarea and rxstreamarea is usable as one streamarea by overlaying them. ? the post**ptr and used**ptr of the rxheaderarea, rxorbarea, txstreamarea, and rxstreamarea monitor the used condition in each area. (in the case of the rx of 1394, the free space of the above two is monitored and the busy_a, b, x is controlled by hardware.) ? by controlling the above functions from the tran & sbp2 control block, a pagetable fetch and data transfer according to sbp-2 are executable by hardware. 7.1.2 ieee1394link/transaction controller xcsbuf area (sram) txheaderarea 8kbytes 0x400000 0x4000c0 0x4000e0 0x400100 (rxheaderareastart) rxorbareastart txheaderareastart (txheaderareastart + 0x0040) txstreamareastart txstreamareaend rxstreamareastart hw_rxheaderarea hw_pagetablearea hw_txheaderarea hw_rxheaderarea rxheaderarea (ringbuffer) rxorbarea (ringbuffer) txheaderarea (2 headers) txorbarea (ringbuffer) notused rxstreamarea (ringbuffer) 0x401fff ide e > 1394 dma area 1394 e > ide dma area used asyncronouse only txareastart + 0x20 + 0x40 asytxpkthdr 1 asytxpkthdr 0 asytxpkthdr 0 txareastart + 0x20 + 0x30 + 0x40 used isocronouse isotxpkthdr 0 isotxpkthdr 1
S1R72801F00A 12 epson 7.2 ieee1394 packet format 7.2.1 transmit packet format (1) txasyncronousepacket <3> quadreadreq, writeresp (2) txasyncronousepacket <4> quadwritereq, quadreadresp, blockreadreq 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 1 2 destinationid sbid speed C CC tl rt pri ack tcode (msb) (msb) (lsb) (lsb) packettypespecinfo reserved 1 quadreadreq (tcode : 0x4) destinationid destinationoffset 1 2 rcode 2 writeresp (tcode : 0x2) destinationid reserved 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 1 2 3 destinationid sbid speed tl rt pri ack tcode (msb) (msb) (lsb) (lsb) packettypespecinfo packettypespecquadletdata reserved 1 quadwritereq (tcode : 0x0) destinationid destinationoffset quadletdata 1 2 3 2 quadreadresp (tcode : 0x6) destinationid reserved quadletdata 1 2 3 (msb) (lsb) 3 blockreadreq (tcode : 0x5) destinationid destinationoffset datalength extendedtcode rcode ee e
S1R72801F00A epson 13 (3) txasyncronousepacket <5> blockwritereq, blockreadresp, lockreq, lockresp (4) txasyncronousephypacket (tcode : 0xe) (5) txisocoronousepacket (tcode : 0xa) name bit count description ack 4 received ackcode 4'h1 ask_complete 4'h2 ask_pending 4'h4 ask_busy_x 4'h5 ask_busy_a 4'h6 ask_busy_b 4'hb ask_tardy 4'hc ask_confilict_error 4'hd ask_data_error 4'he ask_type_error 4'hf ask_address_error all other value reserved transmit packet common format name bit count description speed 3 speed code 3'b000 s100 3'b001 s200 3'b010 s400 all other value reserved sbid 1 souce bus id 0:3ffh, 1:source id 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 1 2 destinationid datalength speed tl rt pri ack tcode (msb) (msb) (lsb) (lsb) packettypespecinfo *datapointer reserved extendedtcode 1 blockwritereq lockreq (tcode : 0x1) (tcode : 0x9) destinationid destinationoffset 1 2 rcode 2 blockreadresp lockresp (tcode : 0x7) (tcode : 0xb) destinationid reserved ee e sbid 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 0x0 reserved reserved tcode (0xe) phypacket reserved ee sbid 0 1 2 3 b.31 24 23 16 15 8 b.0 7 datalength speed tag channel sy tcode (0xa) *datapointer reserved reserved ee sbid
S1R72801F00A 14 epson 7.2.2 receive packet format (1) rxasyncronousepacket <4> quadreadreq, writeresp (2) rxasyncronousepacket <5> quadwritereq, quadreadresp, blockreadreq 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 2 3 destinationid sourceid speed tl bt 0 bc 0 as rt ack pri tcode (msb) (msb) (lsb) (lsb) packettypespecinfo reserved 1 quadreadreq (tcode : 0x4) sourceid destinationoffset 2 3 rcode 2 writeresp (tcode : 0x2) sourceid reserved ee 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 destinationid sourceid speed tl bt 0 bc 0 as rt ack pri tcode (msb) (lsb) packettypespecinfo packettypespecquaddata reserved 2 3 4 (msb) (lsb) 1 quadwritereq (tcode : 0x0) sourceid destinationoffset quadletdata 2 3 4 2 quadreadresp (tcode : 0x6) sourceid reserved quadletdata 2 3 4 (msb) (lsb) 3 blockreadreq (tcode : 0x5) sourceid destinationoffset datalength extendedtcode rcode ee
S1R72801F00A epson 15 (3) rxasyncronousepacket <6> blockwritereq, blockreadresp, lockreq, lockresp (4) rxasyncronousephypacket normal (tcode : 0xe) (5) selfidpacket received selfid packets between busreset and 1st-arbrstgap (tcode : 0xe) 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 2 3 destinationid sourceid datalength speed tl bt 0 bc 0 as rt ack pri tcode (msb) (msb) (lsb) (lsb) packettypespecinfo *datapointer extendedtcode reserved 1 blockwritereq lockreq (tcode : 0x1) (tcode : 0x9) sourceid destinationoffset 2 3 rcode 2 blockreadresp lockresp (tcode : 0x7) (tcode : 0xb) sourceid reserved e e 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 0 x 0 bt 0 1 0 as ack reserved tcode (0xe) phypacket reserved reserved eee 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 bt 1 1 0 as ack reserved tcode (0xe) *datapointer reserved reserved datalength ee
S1R72801F00A 16 epson (6) rxisocronousepacket (tcode : 0xa) 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.0 7 bt 0 1 0 as ack sy tcode (0xa) tag channel *datapointer reserved speed datalength 0 b.31 24 23 16 15 8 b.0 7 bt si bc hc as ack speed C CCC CC receive packet common format name bit count description speed 3 speed code (note 1) as 1 areastatus bit (1: streamarea, 0: orbarea) bt 1 bit which toggles during the busreset period. si 1 whether the received packet is a self id packet bc 1 whether the received packet is a broadcast packet. hc 1 presence/absence of the header crc error (1: packet disabled) ack 4 transmitted ackcode (note 2) psts 4 ackcode which was scheduled to be transmitted (note 2) (note 1) refer to the transmit packet common spd (speed code). (note 2) refer to the transmit packet common ack (ackcode).
S1R72801F00A epson 17 7.3 ieee1394 hardware sbp-2 control the hardware sbp2 of this ic automatically executes a pagetable fetch and data transfer according to the serial bus protocol 2 after receiving specifications of its pagetable size and address. the control of the sbp2 is performed by accessing the internal register. data transfer is controlled by the transmission and reception of signals to and from the phy-link interface and the transmission/reception of a series of packets are automatically executed by having access to the internal sram area. the functions of this block are as follows. this block, (1) receives specifications of a page table size, page table address, speed code, and max payload size, etc. to automatically execute a pagetable fetch and data transfer according to the serial bus protocol 2. (2) can transfer data the equivalent of max. 24-page elements at one time. if no pagetable exists, you can transfer data by directly specifying a data length as a page table size. (3) allows you to perform the pause, resume, or reset during data transfer. though the register value is retained even after the reset, the state machine is restored to the initial state. you can check transfer condition through the register any time. (4) immediately enters the error pause when an error arises during data transfer by which you can check an error cause through the register. the resume from the error pause will pick up the transaction where the error arose. (5) allows you to transfer data if you specify the omission of the pagetable fetch or page element no. to start data. 7.5 built-in cpu regarding the built-in cpu, refer to the e0c33208/204/ 202 technical manual (and e0c33 family asic macro manual). in the built-in cpu core, however, a dma controller and a/d converter are not integrated; this part is different from the description on the dma controller and a/d converter given in technical manual (and macro manual). a low speed oscillation circuit (osc1) is not available. 7.4 ide interface control this ic contains a block to control the ide interface. its functions are as follows. this block, (1) accesses the ide bus by having access to the program mode of the cpu. the access to the data port of the cpu is available only in pio mode. (2) can monitor various kinds of signals of the ide interface. (3) controls the link-up of function blocks in accordance with the control signals and operation end signal from the dma control circuit. (4) manages the condition of data transfer in dma mode of the ide by the hdmarq/xhdmack signal. (5) reads and writes the data of data bus dd15-0 of ide from and to the fifo in the 1394linkcore by the xhior/xhiow signal. if the fifo becomes full or empty to disable data transfer, this block suspends data transfer with specified timing.
S1R72801F00A 18 epson 7.6 flash controller this ic is provided with a function to perform erase and write to the flash rom. (1) chip erase according to a specified sequence, you can erase all memory cells in the built-in flash rom to put them in 1 status. after erasing the chip, check that the data of all memory cells is 1. (2) sector erase this ic is ready for the sector erase in the unit of 512 words/sector. according to a specified sequence, you can erase all memory cells in the built-in flash rom to put them in 1 status. after erasing the chip, check that the data of all memory cells is 1. (3) write write is complete if you continue writing write data in the unit of word until writing of all sectors (512 words) finishes. on completion of the sector write, compare all data in the sectors with original data for confirmation. you cannot change the data of the memory cell from 0 to 1 by writing.
S1R72801F00A epson 19 8. internal register 8.1 ieee1394 link controller register mapping 8.1.1 register table (the base address of this register is 0x100000.) address register name r/w function relation 0x00 mainintstat r(w) main interrupt status register 0x01 subintstat r(w) sub-interrupt status register 0x02 (reserved) 0x03 dmaintstat r(w) dma interrupt status register 0x04 linkintstat1 r(w) link core interrupt status register 1 0x05 linkintstat0 r(w) link core interrupt status register 0 0x06 phyintstat r(w) phy interrupt status register 0x07 (reserved) 0x08 mainintenb r/w main interrupt enable flag register 0x09 subintenb r/w sub-interrupt enable flag register 0x0a (reserved) 0x0b dmaintenb r/w dma interrupt enable flag register 0x0c linkintenb1 r/w link core interrupt enable flag register 1 0x0d linkintenb0 r/w link core interrupt enable flag register 0 0x0e phyintenb r/w phy interrupt enable flag register 0x0f (reserved) 0x10 chipctl r/w chip control register 0x11 hw_revision r/w hardware revision register 0x12 (reserved) 0x13 (reserved) 0x14 (reserved) 0x15 (reserved) 0x16 (reserved) 0x17 (reserved) 0x18 linkctl_h r/w link core control register higher rank 0x19 linkctl_l r/w link core control register lower rank 0x1a linkstat r link core status read register 0x1b prireqcnt r priority request count register 0x1c retrylimit_h r/w dual retry time set register higher rank 0x1d retrylimit_l r/w dual retry time set register lower rank 0x1e maxretry r/w single retry number set register 0x1f irm_stat r/w irm status register 0x20 node_ids_h r/w node ids status register higher rank 0x21 node_ids_l r/w node ids status register lower rank 0x22 (reserved) 0x23 (reserved) 0x24 phyaccctl_h r/w link core control register middle rank 0x25 phyaccctl_l r/w link core control register lower rank 0x26 phyrdstat_h r link core status read register 0x27 phyrdstat_l r/w priority request count register 0x28 chnlindex r/w iso async stream channel index register 0x29 chnlwindow r/w iso async stream channel window register 0x2a cmprindex r/w compare offset address index register 0x2b cmprw indow r/w compare offset address window register 0x2c cycle_time_h r/w cycle time register higher rank
S1R72801F00A 20 epson address register name r/w function relation 0x2d cycle_time_mh r/w cycle time register 0x2e cycle_time_ml r/w cycle time register 0x2f cycle_time_l r/w cycle time register lower rank 0x30 hwsbp2ctl r/w hardware sbp2 control register 0x31 hwsbp2stat r/w hardware sbp2 status read register 0x32 hwsbp2intstat r(w) hardware sbp2 interrupt status register 0x33 hwsbp2index r/w hardware sbp2 index register 0x34 hwsbp2window_h r/w hardware sbp2 window register higher rank 0x35 hwsbp2window_l r/w hardware sbp2 window register lower rank 0x36 payloadsize_h r/w hardware sbp2 payload size set register higher rank 0x37 payloadsize_l r/w hardware sbp2 payload size set register lower rank 0x38 pagetablesize_h r/w hardware pagetable size set register higher rank 0x39 pagetablesize_l r/w hardware pagetable size set register lower rank 0x3a pagetableadrs0 r/w hardware sbp2 pagetable address set register higher rank 0x3b pagetableadrs1 r/w hardware sbp2 pagetable address set register 0x3c pagetableadrs2 r/w hardware sbp2 pagetable address set register 0x3d paqetableadrs3 r/w hardware sbp2 pagetable address set register 0x3e pagetableadrs4 r/w hardware sbp2 pagetable address set register 0x3f pagetableadrs5 r/w hardware sbp2 pagetable address set register lower rank 0x40 linkrxhdrptr_h r/w receive header link pointer register higher rank 0x41 linkrxhdrptr_l r/w receive header link pointer register lower rank 0x42 linkrxorbptr_h r/w receive orb data link pointer register higher rank 0x43 linkrxorbptr_l r/w receive orb data link pointer register lower rank 0x44 linkrxstreamptr_h r/w receive stream data link pointer register higher rank 0x45 linkrxstreamptr_l r/w receive stream data link pointer register lower rank 0x46 linktxstreamptr_h r receive stream data link pointer register higher rank 0x47 linktxstreamptr_l r receive stream data link pointer register lower rank 0x48 usedrxhdrptr_h r/w used receive header pointer register higher rank 0x49 usedrxhdrptr_l r/w used receive header pointer register lower rank 0x4a usedrxorbptr_h r/w used receive orb data pointer register higher rank 0x4b usedrxorbptr_l r/w used receive orb data pointer register lower rank 0x4c ide_rxstreamptr_h r/w receive stream data ide pointer register higher rank 0x4d ide_rxstreamptr_l r/w receive stream data ide pointer register lower rank 0x4e ide_txstreamptr_h r/w receive stream data ide pointer register higher rank 0x4f ide_txstreamptr_l r/w receive stream data ide pointer register lower rank 0x50 bufcontrol r/w buffer control register 0x51 bufmonitor r buffer monitor register 0x52 asydmactl r/w async txdma control register 0x53 isodmactl r/w iso txdma control register 0x54 rxdmactl r/w rxdma control register 0x55 areaindex r/w memory map area set index register 0x56 areawindow_h r/w memory map area set window register higher rank 0x57 areawindow_l r/w memory map area set window register lower rank 0x58 brsthdrptr_h r bus reset header pointer register higher rank 0x59 brsthdrptr_l r bus reset header pointer register lower rank 0x5a brstorbptr_h r bus reset orb pointer register higher rank 0x5b brstorbptr_l r bus reset orb pointer register lower rank 0x5c (reserved) 0x5d (reserved) 0x5e maintctl_h r/w maintenance control register higher rank 0x5f maintctl_l r/w maintenance control register lower rank
S1R72801F00A epson 21 address register name r/w function relation 0x60 ide_config0 r/w ide configuration register 0x61 ide_config1 r/w ide configuration register 0x62 ide_regacccyc r/w ide register access cycle register 0x63 ide_piodmacyc r/w ide pio/dma cycle register 0x64 ide_ultradmacyc r/w ide ultra dma cycle register 0x65 ide_dmactl r/w ide dma control register 0x66 ide_busstat r/w ide bus status read register 0x67 ide_dmastat r/w ide dma status register 0x68 ide_bytecount0 r/w ide byte count set register higher rank 0x69 ide_bytecount1 r/w ide byte count set register 0x6a ide_bytecount2 r/w ide byte count set register 0x6b ide_bytecount3 r/w ide byte count set register lower rank 0x6c ide_crc0 r crc read register higher rank 0x6d ide_crc1 r crc read register lower rank 0x6e (reserved) 0x6f (reserved) 0x70 ide_cs00 r/w ide command block register 0x71 ide_cs01 r/w ide command block register 0x72 ide_cs02 r/w ide command block register 0x73 ide_cs03 r/w ide command block register 0x74 ide_cs04 r/w ide command block register 0x75 ide_cs05 r/w ide command block register 0x76 ide_cs06 r/w ide command block register 0x77 ide_cs07 r/w ide command block register 0x78 ide_cs10 r/w ide command control register 0x79 ide_cs11 r/w ide command control register 0x7a ide_cs12 r/w ide command control register 0x7b ide_cs13 r/w ide command control register 0x7c ide_cs14 r/w ide command control register 0x7d ide_cs15 r/w ide command control register 0x7e ide_cs16 r/w ide command control register 0x7f ide_cs17 r/w ide command control register
S1R72801F00A 22 epson 8.1.2 register/bit table the base address of this register is 0x100000. address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 mainintstat subintstat txisocmp rxdmacmp txasycmp hwsbp2cmp ide_dmacm ide_intrq busreset 0x01 subintstat selfiddone selfiderr hwsbp2err hwsbp2brs linkintstat1 linkintstat0 phyintstat dmaintstat 0x02 (reserved) 0x03 dmaintstat txasyrtygo txasybcsent rxdmafaild txasyfaild txisofaild txasybrabort txasymiss 0x04 linkintstat1 rxontardy rxhcrcerr rxunktcode txrtyexced 0x05 linkintstat0 unexpch duplich isoarbfaild cyctoolong cycoverflw cycevent cyclost cycarbfail 0x06 phyintstat subgap arbgap phy_int phywrdone phyrddone 0x07 (reserved) 0x08 mainintenb ensubintstat entxisocmp enrxdmacmp entxasycmp enhwsbp2cm enide_dmac enide_intrq enbusreset 0x09 subintenb enselfiddone enselfiderr enhwsbp2err enhwsbp2brst enlinkintstat1 enlinkintstat0 enphyintstat endmaintstat 0x0a (reserved) 0x0b dmaintenb entxasyrtygo entxasybcse enrxdmafaild entxasyfaild entxisofaild entxasybrab entxasymiss 0x0c linkintenb1 enrxontardy enrxhcrcerr enrxunktcod entxrtyexced 0x0d ultradmamode enunexpch enduplich enisoarbfaild encyctoolon encycoverflw encycevent encyclost encycarbfail 0x0e phyintenb ensubgap enarbgap enphy_int enphywrdone enphyrddone 0x0f (reserved) 0x10 chipctl suspend ide_mdlrst sendtardy softreset 0x11 hw_revision hw_revision[7:0] 0x12 apetustestoutput_h 0x13 apetustestoutput_l 0x14 lctestindex chip test register 0x15 lctestwindow 0x16 sbp2testindex 0x17 sbp2testwindow 0x18 linkctl_h passselfid passphypkt passbrpkt enposwb enposwq aphy enacc cmstr 0x19 linkctl_l enlink plifrst ignrbchdr ignrbcdata rxbusymode dualrtyenb singlrtyenb 0x1a linkstat id_valid root cablpwsts 0x1b prireqcnt priority budget request count [5:0] 0x1c retrylimit_h seclimit[2:0] cyclimit[12:8] 0x1d retrylimit_l cyclimit[7:0] 0x1e maxretry maxretry[3:0] 0x1f irm_stat noirm wonirm irm_id[5:0] 0x20 node_ids_h busid[9:2] 0x21 node_ids_l busid[1:0] physical id[5:0] 0x22 (reserved) 0x23 (reserved) 0x24 phyaccctl_h rdreq wrreq request address[3:0] 0x25 phyaccctl_l write data[7:0] 0x26 phyrdstat_h read address[3:0] 0x27 phyrdstat_l read data[7:0] 0x28 chnlindex channel index 0x29 chnlwindow channel window 0x2a cmprindex compare address index 0x2b cmprwindow compare address window 0x2c cycle_time_h cycle second[6:0] cyccnt[12] 0x2d cycle_time_mh cycle count[11:4] 0x2e cycle_time_ml cycle count[3:0] cycle offset[11:8] 0x2f cycle_time_l cycle offset[7:0]
S1R72801F00A epson 23 address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x30 hwsbp2ctl ptnotpresen hosttodev fromstream hwsbp2rst hwsbp2rsu hwsbp2pau hwsbp2star 0x31 hwsbp2stat fwpause errpause waitplread hwsbp2exe ptaskexec sttaskexec tranexec 0x32 hwsbp2intstat splittimeout txackedilleg txackmiss brabort rxnotrespcm rxbroadcast rxackdataerr 0x33 hwsbp2index hwsbp2 index 0x34 hwsbp2window_h (msb) hwsbp2 window 0x35 hwsbp2window_l (lsb) 0x36 payloadsize_h (msb) payload size 0x37 payloadsize_l (lsb) 0x38 pagetablesize_h (msb) page table size 0x39 pagetablesize_l (lsb) 0x3a pagetableadrs0 (msb) 0x3b pagetableadrs1 0x3c pagetableadrs2 page table offset address 0x3d paqetableadrs3 0x3e pagetableadrs4 0x3f pagetableadrs5 (lsb) 0x40 linkrxhdrptr_h linkrxhdrptr[12:8] 0x41 linkrxhdrptr_l linkrxhdrptr[7:5] 0x42 linkrxorbptr_h linkorbpointer[12:8] 0x43 linkrxorbptr_l linkrxorbptr[7:2] 0x44 linkrxstreamptr_h linkrxstreamptr[12:8] 0x45 linkrxstreamptr_l linkrxstreamptr[7:2] 0x46 linktxstreamptr_h linktxstreamptr[12:8] 0x47 linktxstreamptr_l linktxstreamptr[7:2] 0x48 usedrxhdrptr_h usedrxhdrptr[12] 0x49 usedrxhdrptr_l usedrxhdrptr[7:5] 0x4a usedrxorbptr_h usedrxorbptr[12:8] 0x4b usedrxorbptr_l usedrxorbptr[7:2] 0x4c ide_rxstreamptr_h ide_rxstreamptr[12:8] 0x4d ide_rxstreamptr_l ide_rxstreamptr[7:2] 0x4e ide_txstreamptr_h ide_txstreamptr[12:8] 0x4f ide_txstreamptr_l ide_txstreamptr[7:2] 0x50 bufcontrol txstreamclr rxstreamclr rxorbclr rxhdrclr updlinktxstrm 0x51 bufmonitor rxpayldrdy txpayldrdy rxhdrremain rxorbfull rxstreamfull rxhdrfull 0x52 asydmactl asychnlsel blkwrareasel asyfifoepty asyfifoclr asytxmon asystart 0x53 isodmactl isochnlsel seltxptr isofifoepty isofifoclr isotxmon isostart 0x54 rxdmactl rxfifoepty rxfifoclr rxmon forcebusy 0x55 areaindex memory map area index 0x56 areawindow_h (msb) memory map area window 0x57 areawindow_l (lsb) 0x58 brsthdrptr_h busreset header pointer[12:8] 0x59 brsthdrptr_l busresetheaderpointer[7:5] 0x5a brstorbptr_h busresetorbpointer[12:8] 0x5b brstorbptr_l busresetorbpointer[7:2] 0x5c (reserved) 0x5d (reserved) 0x5e maintctl_h e_hcrc e_dcrc no_pkt f_ack n_ack 0x5f maintctl_l ack[7:0]
S1R72801F00A 24 epson address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x60 ide_config0 ultradmamode dmamode actport ide_slave dmarq_leve swap 0x61 ide_config1 ide_reset 0x62 ide_regacccyc assert pulse[3:0] negate pulse[3:0] 0x63 ide_piodmacyc assert pulse[3:0] negate pulse[3:0] 0x64 ide_ultradmacyc cycle time[3:0] 0x65 ide_dmactl crc_clear fifo_clear ide_abort ide_directio dmastart 0x66 ide_busstat dmarq dmack intrq iordy diag dasp 0x67 ide_dmastat dmapause dmarun 0x68 ide_bytecount0 (msb) 0x69 ide_bytecount1 ide dma xfer byte count 0x6a ide_bytecount2 0x6b ide_bytecount3 (lsb) 0x6c ide_crc0 (msb) ultra dma crc value 0x6d ide_crc1 (lsb) 0x6e ide_testindex chip test register 0x6f ide_testwindow 0x70 ide_cs00 command block register r- data w- data 0x71 ide_cs01 command block register r- error w- features 0x72 ide_cs02 command block register r- sector count w- sector count 0x73 ide_cs03 command block register r- sector number/lba[bit0-7] w- sector number/lba[bit0-7] 0x74 ide_cs04 command block register r- cylinder low/lba[bit8-15] w- cylinder low/lba[bit8-15] 0x75 ide_cs05 command block register r- cylinder high/lba[bit[16-23] w- cylinder high/lba[bit[16-23] 0x76 ide_cs06 command block register r- device/head,lba[bit24-27] w- device/head,lba[bit24-27] 0x77 ide_cs07 command block register r- status w- command 0x78 ide_cs10 control block register r- data bus hi-impedence w- not used 0x79 ide_cs11 control block register r- data bus hi-impedence w- not used 0x7a ide_cs12 control block register r- data bus hi-impedence w- not used 0x7b ide_cs13 control block register r- data bus hi-impedence w- not used 0x7c ide_cs14 control block register r- data bus hi-impedence w- not used 0x7d ide_cs15 control block register r- data bus hi-impedence w- not used 0x7e ide_cs16 control block register r- alternate status w- device control 0x7f ide_cs17 control block register r- (obsolete) w- not used linkchnnel index/window register chnlindex chnlwindow bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 channelavailableh0 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x01 channelavailableh1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x02 channelavailableh2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x03 channelavailableh3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x04 channelavailablel0 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x05 channelavailablel1 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x06 channelavailablel2 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x07 channelavailablel3 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 0x08 receivechannel0 ch00 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x09 receivechannel1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x0a receivechannel2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x0b receivechannel3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x0c receivechannel4 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x0d receivechannel5 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x0e receivechannel6 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x0f receivechannel7 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63
S1R72801F00A epson 25 compare address index/window register cmprindex chnlwindow bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 comparedoffset0 (msb) 0x01 comparedoffset1 0x02 comparedoffset2 compare destination offset address[47:0] 0x03 comparedoffset3 0x04 comparedoffset4 0x05 comparedoffset5 (lsb) 0x06 (reserved) : (reserved) 0x0f (reserved) h/w sbp2 index chnnel/window register sbp2index sbp2window_h/l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 pageboundary pageboundary[2:0] pageelementnunber pageelementnumber[4:0] 0x01 pgelmentremain_h (msb) page element remain length (bytes) pgelmentremain_l (lsb) 0x02 speedcode speedcode[2:0] maxpayload maxpayload[3:0] 0x03 destinationid_h (msb) destinationid_l destination_id value (lsb) 0x04 splittime_h second[2:0] cycle count[12:8] splittime_l cycle count[7:0] 0x05 (reserved) : (reserved) 0x0f (reserved) memory map area index/window register areaindex areawindow_h/l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 rxorbareastart_h (msb) rxorbareastart[12:8] rxorbareastart_l rxorbareastart[7:2] (lsb) 0x01 txhdrareastart_h (msb) txhdrareastart[12:8] txhdrareastart_l txhdrareastart[7:2] (lsb) 0x02 txstreamareastart_h (msb) txstreamareastart[12:8] txstreamareastart_l txstreamareastart[7:2] (lsb) 0x03 txstreamareaend_h (msb) txstreamareaend[12:8] txstreamareaend_l txstreamareaend[7:2] (lsb) 0x04 rxstreamareastart_h (msb) rxstreamareastart[12:8] rxstreamareastart_l rxstreamareastart[7:2] (lsb) 0x05 (reserved) : (reserved) 0x0f (reserved)
S1R72801F00A 26 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x00 mainintstat 7:subintstat r(w) 0: none 1: sub interrupt occurred 6: txisocmp r(w) 0: none 1: iso pkt transmit done 5: rxdmacmp r(w) 0: none 1: packet reception 4: txasycmp r(w) 0: none 1: ackcode reception 0x00 0x00 C 3: hwsbp2cmp r(w) 0: none 1: hwsbp2 process complete 2: ide_dmacmp r(w) 0: none 1: ide dma transmit complete 1: ide_intrq r(w) 0: none 1: ide interface interrupt 0: busreset r(w) 0: none 1: bas reset detected 0x01 subintstat 7: selfiddone r(w) 0: none 1: self-id phase done 6: selfiderr r(w) 0: none 1: self-id packet error 5: hwsbp2err r(w) 0: none 1: hw sbp2 error 4: hwsbp2brst r(w) 0: none 1: busreset in process hwsbp 0x00 0x00 C 3: linkintstat1 r(w) 0: none 1: link1 interrupt occurred 2: linkintstat0 r(w) 0: none 1: link0 interrupt occurred ultradmamode 1: phyintstat r(w) 0: none 1: phy interrupt occurred 0: dmaintstat r(w) 0: none 1: dma interrupt occurred 0x02 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x03 dmaintstat 7: 0: 1: 6: txasyrtygo r(w) 0: none 1: async tx retry go 5: txasybcsent r(w) 0: none 1: asynctxbroadcast sent 4: rxdmafaild r(w) 0: none 1: rx dma failed 0x00 0x00 C 3: txasyfaild r(w) 0: none 1: async tx failed 2: txisofaild r(w) 0: none 1: iso tx failed 1: txasybrabort r(w) 0: none 1: async tx busreset abort 0: txasymiss r(w) 0: none 1: asynctxackcodemissing 0x04 linkintstat1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 1: 0x00 0x00 C 3: rxontardy r(w) 0: none 1: ack_tardy sent 2: rxhcrcerr r(w) 0: none 1: rx packet header crc err 1: rxunktcode r(w) 0: none 1: rx packet tcode unknown 0: txrtyexced r(w) 0: none 1: tx retry exceeded 0x05 linkintstat0 7: unexpch r(w) 0: none 1: unknown expected channel 6: duplich r(w) 0: none 1: duplicatechanneldetected 5: isoarbfaild r(w) 0: none 1: iso arbtration failed 4: cyctoolong r(w) 0: none 1: iso arbitration failed 0x00 0x00 C 3: cycoverflw r(w) 0: none 1: cycle timer over fullow 2: cycevent r(w) 0: none 1: local cycle event occured 1: cyclost r(w) 0: none 1: cycle start packet lost 0: cycarbfail r(w) 0: none 1: cyclestartpkt arbtration fail 0x06 phyintstat 7: subgap r(w) 0: none 1: sub action gap detected 6: arbgap r(w) 0: none 1: arbtrationresetgapdetected 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: phy_int r(w) 0: none 1: phy interrupt detected 1: phywrdone r(w) 0: none 1: phy register write done 0: phyrddone r(w) 0: none 1: phy register read done 0x07 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 8.1.3 register map (the base address of this register is 0x100000.)
S1R72801F00A epson 27 address register name bit symbol r/w description h.rst s.rst b.rst 0x08 mainintenb 7: ensubintstat r/w 0: disable 1: enable 6: entxisocmp r/w 0: disable 1: enable 5: enrxdmacmp r/w 0: disable 1: enable 4: entxasycmp r/w 0: disable 1: enable 0x00 0x00 C 3: enhwsbp2cmp r/w 0: disable 1: enable 2: enide_dmacmp r/w 0: disable 1: enable 1: enide_intrq r/w 0: disable 1: enable 0: enbusreset r/w 0: disable 1: enable 0x09 subintenb 7: enselfiddone r/w 0: disable 1: enable 6: enselfiderr r/w 0: disable 1: enable 5: enhwsbp2err r/w 0: disable 1: enable 4: enhwsbp2brst r/w 0: disable 1: enable 0x00 0x00 C 3: enlinkintstat1 r/w 0: disable 1: enable 2: enlinkintstat0 r/w 0: disable 1: enable 1: enphyintstat r/w 0: disable 1: enable 0: endmaintstat r/w 0: disable 1: enable 0x0a (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x0b dmaintenb 7: 0: 1: 6: entxasyrtygo r/w 0: disable 1: enable 5: entxasybcsent r/w 0: disable 1: enable 4: enrxdmafaild r/w 0: disable 1: enable 0x00 0x00 C 3: entxasyfaild r/w 0: disable 1: enable 2: entxisofaild r/w 0: disable 1: enable 1: entxasybrabort r/w 0: disable 1: enable 0: entxasymiss r/w 0: disable 1: enable 0x0c linkintenb1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: enrxontardy r/w 0: disable 1: enable 2: enrxhcrcerr r/w 0: disable 1: enable 1: enrxunktcode r/w 0: disable 1: enable 0: entxrtyexced r/w 0: disable 1: enable 0x0d linkintenb0 7: enunexpch r/w 0: disable 1: enable 6: enduplich r/w 0: disable 1: enable 5: enisoarbfaild r/w 0: disable 1: enable 4: encyctoolong r/w 0: disable 1: enable 0x00 0x00 C 3: encycoverflw r/w 0: disable 1: enable 2: encycevent r/w 0: disable 1: enable 1: encyclost r/w 0: disable 1: enable 0: encycarbfail r/w 0: disable 1: enable 0x0e phyintenb 7: ensubgap r/w 0: disable 1: enable 6: enarbgap r/w 0: disable 1: enable 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: enphy_int r/w 0: disable 1: enable 1: enphywrdone r/w 0: disable 1: enable 0: enphyrddone r/w 0: disable 1: enable 0x0f (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1:
S1R72801F00A 28 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x10 chipctl 7: suspend r/w 0: resume 1: suspend 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: ide_mdlrst w 0: none 1: ide_module reset 1: sendtardy r/w 0: none 1: send ack_tardy 0: softreset w 0: none 1: reset start 0x11 hw_revision 7: hw_revision[7] 6: hw_revision[6] 5: hw_revision[5] 4: hw_revision[4] r indicate hard ware revison number 0x03 0x03 0x03 3: hw_revision[3] 2: hw_revision[2] ultradmamode 1: hw_revision[1] 0: hw_revision[0] 0x12 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x13 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x14 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x15 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x16 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x17 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1:
S1R72801F00A epson 29 address register name bit symbol r/w description h.rst s.rst b.rst 0x18 linkctl_h 7: passselfid 0: non passselfid 1: selfCid to dma fifo 6: passphypkt 0: non pass phy packet 1: phy pkt to dma fifo 5: passbrpkt 0: non pass busrst packet 1: busrst pkt to dma fifo 4: enposwb r/w 0: disable posted wb 1: enable posted wb 0x00 0x00 C 3: enposwq 0: disable poosted wq 1: enable posted wq 2: aphy 0: phy 1394.a uncorrespond 1: phy 1394.a correspond 1: enacc 0: ack acceleration disable 1: ack acceleration enable 0: cmstr 0: cycle master not capabl 1: cycle master capable 0x19 linkctl_l 7: enlink r/w 0: disable link 1: enable link C C 6: 0: 1: 5: plifrst w 0: none 1: reset phy/link i/f 0 C 4: ignrbchdr r/w 0: bc pkt to dma fifo 1: ignore bc packet 0x00 0 C 3: ignrbcdata r/w 0: bc data to dma fifo 1: ignore bcCdata 0 C 2: rxbusymode r/w 0: dual 1: single 0 C 1: dualrtyenb r/w 0: dual retry disable 1: dual retry enable 0 C 0: singlrtyenb r/w 0: single retry disable 1: single retry enable 0 C 0x1a linkstat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 C C 3: 0: 1: 2: id_valid r 0: phyid invalid 1: phyid valid 1: root r 0: self node = not root 1: self node = root 0: cablpwsts r 0: cable power status ng 1: cable power status ok 0x1b prireqcnt 7: 0: 1: 6: 0: 1: 5: prireq[5] 4: prireq[4] 0x00 0x00 0x00 3: prireq[3] r/w maximum number of certain priority arb request 2: prireq[2] 1: prireq[1] 0: prireq[0] 0x1c retrylimit_h 7: seclimit[2] dual phase retry limit 6: seclimit[1] r/w second limit 5: seclimit[0] 4: cyclimt[12] 0x00 0x00 C 3: cyclimt[11] 2: cyclimt[10] 1: cyclimt[9] 0: cyclimt[8] 0x1d retrylimit_l 7: cyclimt[7] r/w cycle limit 6: cyclimt[6] 5: cyclimt[5] if (seclimit == 0 and cyclimit==0) 4: cyclimt[4] dual phase is ignore 0x00 0x00 C 3: cyclimt[3] 2: cyclimt[2] 1: cyclimt[1] 0: cyclimt[0] 0x1e maxretry 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: maxrty[3] single phase retry limit 2: maxrty[2] r/w max retry count value 1: maxrty[1] if maxrty == 0, single phase retry is ignore 0: maxrty[0] 0x1f irm_stat 7: noirm r 0: exist irm node 1: none irm node 6: wonirm r(w) 0: other node 1: self node 5: irmid[5] 4: irmid[4] physical id of irm node 0x3f C 0x3f 3: irmid[3] r no exist irm node then irmid= 0x3f 2: irmid[2] 1: irmid[1] 0: irmid[0]
S1R72801F00A 30 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x20 node_ids_h 7: busid[9] 6: busid[8] 5: busid[7] serial bus id number 4: busid[6] single bus, bus id = 0x3ff 0xff C C 3: busid[5] r/w multiple bus, bus id is uniquely specifying 2: busid[4] 1: busid[3] 0: busid[2] 0x21 node_ids_l 7: busid[1] C 6: busid[0] C 5: phyid[5] 1 4: phyid[4] 0xff C 1 3: phyid[3] r self node's physical id number 1 2: phyid[2] 1 ultradmamode 1: phyid[1] 1 0: phyid[0] 1 0x22 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x23 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x24 phyaccctl_h 7: rdreq r/w 0: normal 1: phy reg rd request 6: wrreq r/w 0: normal 1: phy reg wr request 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: reqadd[3] 2: reqadd[2] r/w phy register read/write request address 1: reqadd[1] 0: reqadd[0] 0x25 phyaccctl_l 7: wrdat[7] 6: wrdat[6] 5: wrdat[5] 4: wrdat[4] r/w phy register write data 0x00 0x00 C 3: wrdat[3] 2: wrdat[2] 1: wrdat[1] 0: wrdat[0] 0x26 phyrdstat_h 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rdadd[3] 2: rdadd[2] r phy register read address 1: rdadd[1] 0: rdadd[0] 0x27 phyrdstat_l 7: rddat[7] 6: rddat[6] 5: rddat[5] 4: rddat[4] r phy register read data 0x00 0x00 C 3: rddat[3] 2: rddat[2] 1: rddat[1] 0: rddat[0]
S1R72801F00A epson 31 address register name bit symbol r/w description h.rst s.rst b.rst 0x28 chnlindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: channel index[3] 2: channel index[2] r/w iso (async stream) channel index 1: channel index[1] 0: channel index[0] 0x29 chnlwindow 7: channel window[7] 6: channel window[6] 5: channel window[5] 4: channel window[4] r/w iso (async stream) 0x00 0x00 C 3: channel window[3] cahnnel window 2: channel window[2] 1: channel window[1] 0: channel window[0] 0x2a cmprindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: compare index[3] 2: compare index[2] r/w compare address index 1: compare index[1] 0: compare index[0] 0x2b cmprwindow 7: compare window[7] 6: compare window[6] 5: compare window[5] 4: compare window[4] r/w compare address window 0x00 0x00 C 3: compare window[3] 2: compare window[2] 1: compare window[1] 0: compare window[0] 0x2c cycle_time_h 7: cycle second[6] 6: cycle second[5] 5: cycle second[4] 4: cycle second[3] r/w cycle_time.second_count 0x00 C C 3: cycle second[2] 2: cycle second[1] 1: cycle second[0] 0: cycle count[12] 0x2d cycle_time_mh 7: cycle count[11] 6: cycle count[10] 5: cycle count[9] 4: cycle count[8] 0x00 C C 3: cycle count[7] 2: cycle count[6] r/w cycle_time.cycle_count 1: cycle count[5] 0: cycle count[4] 0x2e cycle_time_ml 7: cycle count[3] 6: cycle count[2] 5: cycle count[1] 4: cycle count[0] 0x00 C C 3: cycle offset[11] 2: cycle offset[10] 1: cycle offset[9] 0: cycle offset[8] 0x2f cycle_time_l 7: cycle offset[7] 6: cycle offset[6] r/w cycle_time.cycle_offset 5: cycle offset[5] 4: cycle offset[4] 0x00 C C 3: cycle offset[3] 2: cycle offset[2] 1: cycle offset[1] 0: cycle offset[0]
S1R72801F00A 32 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x30 hwsbp2ctl 7: ptnotpresent r/w 0: present 1: not present 6: hosttodev r/w 0: host device 5: fromstream r/w 0: from pagetable 1: fromstream 4: 0: 1: 0x00 0x00 C 3: hwsbp2rst w 0: none 1: reset 2: hwsbp2rsum w 0: none 1: resume 1: hwsbp2pause w 0: none 1: pause 0: hwsbp2start w 0: none 1: start 0x31 hwsbp2stat 7: fwpause r 0: not firmware pause 1: firmwre pause 6: errpause r 0: not error pause 1: error pause 5: 0: 1: 4: waitplready r 0: not ready 1: ready 0x00 0x00 C 3: hwsbp2exec r 0: stop 1: execute 2: ptaskexec r 0: stop 1: execute ultradmamode 1: sttaskexec r 0: stop 1: execute 0: tranexec r 0: stop 1: execute 0x32 hwsbp2intstat 7: splittimeout r(w) 0: none 1: splittimeout 6: txackedillegal r(w) 0: none 1: txackedillegal 5: txackmiss r(w) 0: none 1: txasymiss 4: brabort r(w) 0: none 1: brabort 0x00 0x00 C 3: 0: 1: 2: rxnotrespcmp r(w) 0: none 1: rxnotrespcmp 1: rxbroadcast r(w) 0: none 1: rxbroadcast 0: rxackdataerr r(w) 0: none 1: rxackdataerr 0x33 hwsbp2index 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: hwsbp2 index[3] 2: hwsbp2 index[2] r/w hwsbp2 index 1: hwsbp2 index[1] 0: hwsbp2 index[0] 0x34 hwsbp2window_h 7: hwsbp2 window [15] 6: hwsbp2 window [14] 5: hwsbp2 window [13] 4: hwsbp2 window [12] 0x00 0x00 C 3: hwsbp2 window [11] 2: hwsbp2 window [10] 1: hwsbp2 window[9] 0: hwsbp2 window[8] r/w hwsbp2 window 0x35 hwsbp2window_l 7: hwsbp2 window[7] 6: hwsbp2 window[6] 5: hwsbp2 window[5] 4: hwsbp2 window[4] 0x00 0x00 C 3: hwsbp2 window[3] 2: hwsbp2 window[2] 1: hwsbp2 window[1] 0: hwsbp2 window[0] 0x36 payloadsize_h 7: payload size[15] 6: payload size[14] 5: payload size[13] 4: payload size[12] 0x00 0x00 C 3: payload size[11] set payload size (bytes) 2: payload size[10] if (hwsbp2ctl.hwsbp2exec ==0) { 1: payload size[9] write is valid. 0: payload size[8] r/w } else { 0x37 payloadsize_l 7: payload size[7] write is invalid. 6: payload size[6] } 5: payload size[5] 4: payload size[4] 0x00 0x00 C 3: payload size[3] 2: payload size[2] 1: payload size[1] 0: payload size[0]
S1R72801F00A epson 33 address register name bit symbol r/w description h.rst s.rst b.rst 0x38 pagetablesize_h 7: page table size [15] 6: page table size [14] 5: page table size [13] 4: page table size [12] if (hwsbp2ctl.ptnotpresent == 0) { 0x00 0x00 C 3: page table size [11] write:set pageelement *8 (bytes) 2: page table size [10] read :indicate page table size 1: page table size[9] } else { 0: page table size[8] r/w write:set data length (bytes) 0x39 pagetablesize_l 7: page table size[7] read :indicate create pageelement *8 (bytes) 6: page table size[6] } 5: page table size[5] 4: page table size[4] 0x00 0x00 C 3: page table size[3] 2: page table size[2] 1: page table size[1] 0: page table size[0] 0x3a pagetableadrs0 7: ptadress[47] 6: ptadress[46] 5: ptadress[45] 4: ptadress[44] 0x00 0x00 C 3: ptadress[43] 2: ptadress[42] 1: ptadress[41] 0: ptadress[40] 0x3b pagetableadrs1 7: ptadress[39] 6: ptadress[38] 5: ptadress[37] 4: ptadress[36] 0x00 0x00 C 3: ptadress[35] 2: ptadress[34] 1: ptadress[33] 0: ptadress[32] 0x3c pagetableadrs2 7: ptadress[31] 6: ptadress[30] 5: ptadress[29] 4: ptadress[28] 0x00 0x00 C 3: ptadress[27] 2: ptadress[26] 1: ptadress[25] 0: ptadress[24] r/w write: set pagetable offset address 0x3d paqetableadrs3 7: ptadress[23] read: indicate nextpagetable offset address 6: ptadress[22] 5: ptadress[21] 4: ptadress[20] 0x00 0x00 C 3: ptadress[19] 2: ptadress[18] 1: ptadress[17] 0: ptadress[16] 0x3e pagetableadrs4 7: ptadress[15] 6: ptadress[14] 5: ptadress[13] 4: ptadress[12] 0x00 0x00 C 3: ptadress[11] 2: ptadress[10] 1: ptadress[9] 0: ptadress[8] 0x3f pagetableadrs5 7: ptadress[7] 6: ptadress[6] 5: ptadress[5] 4: ptadress[4] 0x00 0x00 C 3: ptadress[3] 2: ptadress[2] 1: ptadress[1] 0: ptadress[0]
S1R72801F00A 34 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x40 linkrxhdrptr_h 7: write is ignore 6: read is always zero 5: 4: lrhp[12] 0x00 0x00 C 3: lrhp[11] 2: lrhp[10] 1: lrhp[9] r/w current received packet header area pointer 0: lrhp[8] 0x41 linkrxhdrptr_l 7: lrhp[7] 6: lrhp[6] 5: lrhp[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero ultradmamode 1: 0: 0x42 linkrxorbptr_h 7: write is ignore 6: read is always zero 5: 4: pop[12] 0x00 0x00 C 3: pop[11] 2: pop[10] 1: pop[9] 0: pop[8] 0x43 linkrxorbptr_l 7: pop[7] r/w current received packet orb data area pointer 6: pop[6] 5: pop[5] 4: pop[4] 0x00 0x00 C 3: pop[3] 2: pop[2] 1: write is ignore 0: read is always zero 0x44 linkrxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: psp[12] 0x00 0x00 C 3: psp[11] 2: psp[10] 1: psp[9] 0: psp[8] 0x45 linkrxstreamptr_l 7: psp[7] r/w current received packet stream data area pointer 6: psp[6] 5: psp[5] 4: psp[4] 0x00 0x00 C 3: psp[3] 2: psp[2] 1: write is ignore 0: read is always zero 0x46 linktxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: ptdp[12] 0x00 0x00 3: ptdp[11] 2: ptdp[10] 1: ptdp[9] 0: ptdp[8] 0x47 linktxstreamptr_l 7: ptdp[7] r current transmit packet data area pointer 6: ptdp[6] 5: ptdp[5] 4: ptdp[4] 0x00 0x00 3: ptdp[3] 2: ptdp[2] 1: write is ignore 0: read is always zero
S1R72801F00A epson 35 address register name bit symbol r/w description h.rst s.rst b.rst 0x48 usedrxhdrptr_h 7: write is ignore 6: read always zero 5: 4: urhp[12] 0x00 0x00 C 3: urhp[11] 2: urhp[10] 1: urhp[9] r/w received packet header area used pointer 0: urhp[8] 0x49 usedrxhdrptr_l 7: urhp[7] 6: urhp[6] 5: urhp[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero 1: 0: 0x4a usedrxorbptr_h 7: write is ignore 6: read is always zero 5: 4: uop[12] 0x00 0x00 C 3: uop[11] 2: uop[10] 1: uop[9] 0: uop[8] 0x4b usedrxorbptr_l 7: uop[7] r/w received packet orb data area used pointer 6: uop[6] 5: uop[5] 4: uop[4] 0x00 0x00 C 3: uop[3] 2: uop[2] 1: write is ignore 0: read is always zero 0x4c ide_rxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: irsp[12] 0x00 0x00 C 3: irsp[11] 2: irsp[10] 1: irsp[9] 0: irsp[8] 0x4d ide_rxstreamptr_l 7: irsp[7] r/w received packet stream data area ide pointer 6: irsp[6] 5: irsp[5] 4: irsp[4] 0x00 0x00 C 3: irsp[3] 2: irsp[2] 1: write is ignore 0: read is always zero 0x4e ide_txstreamptr_h 7: write is ignore 6: read is always zero 5: 4: itsp[12] 0x00 0x00 C 3: itsp[11] 2: itsp[10] 1: itsp[9] 0: itsp[8] 0x4f ide_txstreamptr_l 7: itsp[7] r/w transmit packet stream data area ide pointer 6: itsp[6] 5: itsp[5] 4: itsp[4] 0x00 0x00 C 3: itsp[3] 2: itsp[2] 1: write is ignore 0: read is always zero
S1R72801F00A 36 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x50 bufcontrol 7: txstreamclr w 0: none affect 1: tx stream data clear 6: rxstreamclr w 0: none affect 1: rx stream data clear 5: rxorbclr w 0: none affect 1: rx orb dat clear 4: rxhdrclr w 0: none affect 1: rx header clear 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: updlinktxstrm w 0: none affect 1: update link tx stream ptr 0x51 bufmonitor 7: rxpayldrdy r 0: rx payld capa not ready 1: rx payload capa ready 6: txpayldrdy r 0: tx payld capa not ready 1: tx payload capa ready 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rxhdrremain r 0: rx header area empty 1: rx header not empty 2: rxorbfull r 0: rx orb area not full 1: rx orb data area full ultradmamode 1: rxstreamfull r 0: rx stream area not full 1: rx stream data area full 0: rxhdrfull r 0: rx header area not full 1: rx header area full 0x52 asydmactl 7: asychnlsel r/w 0: asytxpkthdr0 1: asytxpkthdr1 6: 0: 1: 5: 0: 1: 4: blkwrareasel r/w 0: rx orb area 1: rx stream area 0x00 0x00 C 3: asyfifoepty r 0: asyfifo empty 1: non empty 2: asyfifoclr w 0: normal 1: asyfifo clear 1: asytxmon r 0: async tx stop 1: async tx run 0: asystart w 0: normal 1: async start 0x53 isodmactl 7: isochnlsel r/w 0: isotxpkthdr0 1: isotxpkthdr1 6: 0: 1: 5: 0: 1: 4: seltxptr r/w 0: async tx pointer select 1: iso tx pointer select 0x00 0x00 C 3: isofifoepty r 0: isofifo empty 1: non empty 2: isofifoclr w 0: normal 1: isofifo clear 1: isotxmon r 0: iso tx stop 1: iso tx run 0: isostart w 0: normal 1: start 0x54 rxdmactl 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rxfifoepty r 0: rx fifo empty 1: non empty 2: rxfifoclr w 0: normal 1: rx fifo clear 1: rxmon r 0: rx stop 1: rx run 0: forcebusy r/w 0: normal 1: busy 0x55 areaindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: memmapindex[3] 2: memmapindex[2] r/w memory map area index 1: memmapindex[1] 0: memmapindex[0] 0x56 areawindow_h 7: memmapwindow[15] 6: memmapwindow[14] 5: memmapwindow[13] 4: memmapwindow[12] 0x00 0x00 C 3: memmapwindow[11] 2: memmapwindow[10] 1: memmapwindow[9] 0: memmapwindow[8] r/w memory map area window 0x57 areawindow_l 7: memmapwindow[7] 6: memmapwindow[6] 5: memmapwindow[5] 4: memmapwindow[4] 0x00 0x00 C 3: memmapwindow[3] 2: memmapwindow[2] 1: memmapwindow[1] 0: memmapwindow[0]
S1R72801F00A epson 37 address register name bit symbol r/w description h.rst s.rst b.rst 0x58 brsthdrptr_h 7: write is ignore 6: read is always zero 5: 4: busresetptr[12] 0x00 0x00 C 3: busresetptr[11] 2: busresetptr[10] 1: busresetptr[9] r bus reset header area pointer 0: busresetptr[8] this register indicates address in rx header area 0x59 brsthdrptr_l 7: busresetptr[7] when busrest detected. 6: busresetptr[6] 5: busresetptr[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero 1: 0: 0x5a brstorbptr_h 7: write is ignore 6: read is always zero 5: 4: busrstorbptr[12] 0x00 0x00 C 3: busrstorbptr[11] 2: busrstorbptr[10] 1: busrstorbptr[9] 0: busrstorbptr[8] 0x5b brstorbptr_l 7: busrstorbptr[7] r bus reset orb-data area pointer 6: busrstorbptr[6] this register indicates address in rx orb data area 5: busrstorbptr[5] when busrest detected. 4: busrstorbptr[4] 0x00 0x00 C 3: busrstorbptr[3] 2: busrstorbptr[2] 1: write is ignore 0: read is always zero 0x5c (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x5d (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x5e maintctl_h 7: e_hcrc r/w 0: 1: add header crc error 6: e_dcrc r/w 0: 1: add data crc error 5: no_pkt r/w 0: 1: no transmit next packet 4: f_ack r/w 0: 1: tx optional ackcode 0x00 0x00 C 3: n_ack r/w 0: 1: no transmit ackpacket 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x5f maintctl_l 7: ack[7] 6: ack[6] 5: ack[5] 4: ack[4] r/w optional ackcode 0x00 0x00 C 3: ack[3] 2: ack[2] 1: ack[1] 0: ack[0]
S1R72801F00A 38 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x60 ide_config0 7: ultradmamode 0: dma mode 1: ultra dma mode 6: dmamode 0: pio mode 1: dma mode 5: actport 0: none 1: active 4: ide_slave r/w 0: master 1: slave 0x00 0x00 C 3: dmarq_level 0: positive logic 1: negative logic 2: swap 0: nomal 1: swap ide port hi & lo 1: 0: 1: 0: 0: 1: 0x61 ide_config1 7: ide_reset r/w 0: none 1: ide reset 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: ultradmamode 1: 0: 1: 0: r/w 0: 1: 0x62 ide_regacccyc 7: assert pulse[3] 6: assert pulse[2] r/w ide register access strobe signal assert pulse 5: assert pulse[1] width minimum value 4: assert pulse[0] 0x00 0x00 C 3: negate pulse[3] 2: negate pulse[2] r/w ide register access strobe signal negate pulse 1: negate pulse[1] width minimum value 0: negate pulse[0] 0x63 ide_piodmacyc 7: assert pulse[3] 6: assert pulse[2] r/w ide transfer mode strobe signal assert pulse 5: assert pulse[1] width minimum value 4: assert pulse[0] 0x00 0x00 C 3: negate pulse[3] 2: negate pulse[2] r/w ide transfer mode strobe signal negate pulse 1: negate pulse[1] width minimum value 0: negate pulse[0] 0x64 ide_ultradmacyc 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: cycle time[3] 0x00 0x00 C 2: cycle time[2] r/w ide ultra dma transfer mode strobe signal 1: cycle time[1] minimum cycle time 0: cycle time[0] 0x65 ide_dmactl 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: crc_clear w 0: none 1: crc clear 0x00 0x00 C 3: fifo_clear w 0: none 1: fifo clear 2: ide_abort w 0: none 1: ide transfer abort 1: ide_direction r/w 0: sram C> ide 1: ide C> sram 0: dmastart w 0: none 1: ide dma start 0x66 ide_busstat 7: dmarq 6: dmack 5: intrq 4: iordy r indicate ide i/f signals state 0x00 0x00 C 3: 2: 1: diag 0: dasp 0x67 ide_dmastat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: dmapause r 0: ide dma not pause 1: ide dma pause 0: dmarun w 0: not dma 1: ide dma running
S1R72801F00A epson 39 address register name bit symbol r/w description h.rst s.rst b.rst 0x68 ide_bytecount0 7: bytecount[31] 6: bytecount[30] 5: bytecount[29] 4: bytecount[28] 0x00 0x00 C 3: bytecount[27] 2: bytecount[26] 1: bytecount[25] 0: bytecount[24] 0x69 ide_bytecount1 7: bytecount[23] 6: bytecount[22] 5: bytecount[21] 4: bytecount[20] 0x00 0x00 C 3: bytecount[19] 2: bytecount[18] r/w ide data transfer byte count register 1: bytecount[17] read: indicate remain byte count 0: bytecount[16] write: set total transfer byte count 0x6a ide_bytecount2 7: bytecount[15] 6: bytecount[14] 5: bytecount[13] 4: bytecount[12] 0x00 0x00 C 3: bytecount[11] 2: bytecount[10] 1: bytecount[9] 0: bytecount[8] 0x6b ide_bytecount3 7: bytecount[7] 6: bytecount[6] 5: bytecount[5] 4: bytecount[4] 0x00 0x00 C 3: bytecount[3] 2: bytecount[2] 1: bytecount[1] 0: bytecount[0] 0x6c ide_crc0 7: crc[15] 6: crc[14] 5: crc[13] 4: crc[12] 0x00 0x00 C 3: crc[11] 2: crc[10] 1: crc[9] 0: crc[8] r ide crc data register 0x6d ide_crc1 7: crc[7] 6: crc[6] 5: crc[5] 4: crc[4] 0x00 0x00 C 3: crc[3] 2: crc[2] 1: crc[1] 0: crc[0] 0x6e ide_testindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 0x6f ide_testwindow 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1:
S1R72801F00A 40 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x70 ide_cs00 7: 6: command block register 5: 4: r/w data register 0x00 0x00 C 3: 2: 1: 0: 0x71 ide_cs01 7: 6: command block register 5: 4: r/w read : error register 0x00 0x00 C 3: write: features register 2: ultradmamode 1: 0: 0x72 ide_cs02 7: 6: command block register 5: 4: r/w sector count register 0x00 0x00 C 3: 2: 1: 0: 0x73 ide_cs03 7: 6: command block register 5: 4: r/w sector number register or 0x00 0x00 C 3: logical block address(lba) bit 0 C 7 2: 1: 0: 0x74 ide_cs04 7: 6: command block register 5: 4: r/w cylinder low register or 0x00 0x00 C 3: logical block address(lba) bit 8 C 15 2: 1: 0: 0x75 ide_cs05 7: 6: command block register 5: 4: r/w cylinder high register or 0x00 0x00 C 3: logical block address(lba) bit 16 C 23 2: 1: 0: 0x76 ide_cs06 7: 6: command block register 5: 4: r/w device/head register 0x00 0x00 0x00 C 3: logical block address(lba) bit 24 C 27 2: 1: 0: 0x77 ide_cs07 7: 6: command block register 5: 4: r/w read : status register 0x00 0x00 0x00 C 3: write: command register 2: 1: 0:
S1R72801F00A epson 41 address register name bit symbol r/w description h.rst s.rst b.rst 0x78 ide_cs10 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x79 ide_cs11 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7a ide_cs12 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7b ide_cs13 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7c ide_cs14 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7d ide_cs15 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7e ide_cs16 7: 6: control block register 5: 4: r/w read : alternate status 0x00 0x00 C 3: write: device control 2: 1: 0: 0x7f ide_cs17 7: 6: control block register 5: 4: r/w read : (obsolete) 0x00 0x00 C 3: write: not used 2: 1: 0:
S1R72801F00A 42 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x00 mainintstat 7:subintstat r(w) 0: none 1: sub interrupt occurred 6: txisocmp r(w) 0: none 1: iso pkt transmit done 5: rxdmacmp r(w) 0: none 1: packet reception 4: txasycmp r(w) 0: none 1: ackcode reception 0x00 0x00 C 3: hwsbp2cmp r(w) 0: none 1: hwsbp2 process complete 2: ide_dmacmp r(w) 0: none 1: ide dma transmit complete 1: ide_intrq r(w) 0: none 1: ide interface interrupt 0: busreset r(w) 0: none 1: bas reset detected 8.1.4 detail description of register (the base address of this register is 0x100000.) main interrupt status register when this ic interrupts the cpu, the cpu first reads this register to handle it, indicating which interrupt status register is a factor of this interrupt. subsequent to reading this register, the subintstat (bit 7) reads an interrupt status register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. after that, it writes the read value to the interrupt status register to clear the bit. in the case the interrupt factor still remains, however, the bit is not cleared. when one of 7 bits of the txisocmp, rxdmacmp, txasycmp, hwsbp2cmp, ide_dmacmp, ide_intrq, and busreset other than above is an interrupt source, this register clears the bit by writing the read value. note) the bits of this register control the xint of output pin. writing to this register negates the xint once even if the interrupt factor remains, asserting the xint after a certain period. (ready for a timer or edge interrupt). bit7 sub interrupt status when an interrupt factor exists at each bit shown at the subintstat register, this bit becomes 1. bit 6 isochronous packet transmit complete when an iso packet transmit is complete, this bit becomes 1. bit5 receive packet dma complete when a received packet is written to the receive buffer area, this bit becomes 1. bit4 asynchronous packet transmit complete when an ack packet to an async transmit packet is received, this bit becomes 1. the ack code is written to the footer area of the transmit packet header. bit 3 hwsbp2 process complete when a hwsbp2 processing is complete, this bit becomes 1. bit2 ide dma transmit complete when an ide i/f dma transmit is complete, this bit becomes 1. bit1 ide interface interrupt when the intrq signal is asserted to the ide i/f, this bit becomes 1. bit0 busreset detected when a busreset signal is detected on the 1394 serial bus, this bit becomes 1. when it issues a busreset, this bit becomes 1 as well.
S1R72801F00A epson 43 sub-interrupt status register the value of each bit of this register indicates the status of a corresponding interrupt source. if these bits become 1 when the associated bit of the subintenb register is 1, this register asserts an interrupt signal to the cpu. the cpu reads this register after receiving the interrupt signal to locate an interrupt source. by writing the read value again, it clears these bits. subsequent to reading this register, the lower order 4 bits reads the interrupt status register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. after that, it writes the read value to the interrupt status register to clear the bit. in the case that the interrupt factor still remains, however, the bit is not cleared. bit7 self identify period complete when a self id period finishes, this bit becomes 1. bit6 self identify packet error when a self-id packet with an error is received during the self-id period or when the self-id period finishes due to an error, this bit becomes 1. bit5 hwsbp2err when an interrupt factor from the hwsbp2 indicated on the hwsbp2intstat register exists, this bit becomes 1. bit4 busreset in process hwsbp2 when a busreset occurs in the hwsbp2 processing, this bit becomes 1. bit3 link core interrupt status1 when an interrupt factor from the link core indicated on the linkintstat1 register exists, this bit becomes 1. bit2 link core interrupt status0 when an interrupt factor from the link core indicated on the linkintstat0 register exists, this bit becomes 1. bit1 phy/link interrupt status when an interrupt factor from the phy status indicated on the phyintstat register exists, this bit becomes 1. bit0 link dma interrupt status when an interrupt factor exists in the internal dma operation indicated on the dmaintstat register, this bit becomes 1. address register name bit symbol r/w description h.rst s.rst b.rst 0x01 subintstat 7: selfiddone r(w) 0: none 1: self-id phase done 6: selfiderr r(w) 0: none 1: self-id packet error 5: hwsbp2err r(w) 0: none 1: hw sbp2 error 4: hwsbp2brst r(w) 0: none 1: busreset in process hwsbp 0x00 0x00 C 3: linkintstat1 r(w) 0: none 1: link1 interrupt occurred 2: linkintstat0 r(w) 0: none 1: link0 interrupt occurred 1: phyintstat r(w) 0: none 1: phy interrupt occurred 0: dmaintstat r(w) 0: none 1: dma interrupt occurred address register name bit symbol r/w description h.rst s.rst b.rst 0x02 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1:
S1R72801F00A 44 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x03 dmaintstat 7: 0: 1: 6: txasyrtygo r(w) 0: none 1: async tx retry go 5: txasybcsent r(w) 0: none 1: asynctxbroadcast sent 4: rxdmafaild r(w) 0: none 1: rx dma failed 0x00 0x00 C 3: txasyfaild r(w) 0: none 1: async tx failed 2: txisofaild r(w) 0: none 1: iso tx failed 1: txasybrabort r(w) 0: none 1: async tx busreset abort 0: txasymiss r(w) 0: none 1: asynctxackcodemissing dma interrupt status register the value of each bit of this register indicates the status of a corresponding interrupt source. if these bits become h when the associated bit of the dmaintenb register is 1, this register asserts the interrupt signal to the cpu. the cpu reads this register after receiving the interrupt signal to locate an interrupt source. by writing the read value again, it clears these bits. bit7 reserved when a sub action gap is detected in phy status of phy/link interface, this bit becomes 1. bit6 transmit async packet retry go when an auto retry is performed after transmitting an async packet and receiving an ack_busy, this bit becomes 1. bit5 transmit async broadcast packet sent after a transmission of a broadcast packet of async or a phy packet finishes, this bit becomes 1. bit4 receive packet link dma failed when a received packet cannot be written to the buffer due to the following reasons, this bit becomes 1. 1) dma was too late. 2) a packet was received when the forcebusy bit is on. bit3 transmit async packet linkdma failed when data cannot be transferred from the buffer to the link core at the time of async packet transmission (dma fifo is under flow), this bit becomes 1. bit2 transmit iso packet linkdma failed when data cannot be transferred from the buffer to the link core at the time of iso packet transmission (dma fifo is under flow), this bit becomes 1. bit 1 transmit async packet busreset abort when a transmit packet is disabled by a busreset before an ack packet is returned at the time of async packet transmission, this bit becomes 1. bit0 transmit async packet ack-code missing when a ack packet is not returned at the time of async packet transmission, this bit becomes 1.
S1R72801F00A epson 45 link core interrupt status register 1 the value of each bit of this register indicates the status of a corresponding interrupt source. if these bits become 1 when the associated bit of the linkintenb1 register is 1, this register asserts the interrupt signal to the cpu. the cpu reads this register after receiving the interrupt signal to locate an interrupt source. by writing the read value again, it clears these bits. bit7 reserved bit6 reserved bit5 reserved bit4 reserved bit3 rxontardy when a packet is received when the chipctl. sendtardy bit is 1, an ack_tardy is returned to the party of the other end and this bit becomes 1. bit2 receive packet header crc error when an error exists in the header crc of a received packet, this bit becomes 1. bit1 receive packet tcode unknown when the tcode in a received packet is invalid, this bit becomes 1. bit0 transmit retry exceeded if a transmit retry fails since the set value of the maxretry register is exceeded when the retrylimit register is not zero or the maxretry register is not 0 and this bit becomes 1. address register name bit symbol r/w description h.rst s.rst b.rst 0x04 linkintstat1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rxontardy r(w) 0: none 1: ack_tardy sent 2: rxhcrcerr r(w) 0: none 1: rx packet header crc err 1: rxunktcode r(w) 0: none 1: rx packet tcode unknown 0: txrtyexced r(w) 0: none 1: tx retry exceeded
S1R72801F00A 46 epson link core interrupt status register 0 the value of each bit of this register indicates the status of a corresponding interrupt source. if these bits become 1 when the associated bit of the linkintenb0 register is 1, this register asserts the interrupt signal to the cpu. the cpu reads this register after receiving the interrupt signal to locate an interrupt source. by writing the read value again, it clears these bits. bit7 unknown expected channel when a packet of iso channel not set in the channel_available register is detected, this bit becomes 1. it is enabled when the wonirm = 1 of irm idstat register (the self node is irm). bit6 duplicatechanneldetected when a packet of a same channel is detected in the iso period of 1 cycle, this bit becomes 1. it is enabled when the wonirm = 1 of irm idstat register (the self node is irm). bit5 iso arbitration failed when an iso packet transmit request is received but a subaction gap is detected before it is transmitted, this bit becomes 1. bit4 iso arbitration failed when a cycle_start packet is received but a subaction gap cannot be detected even after the isochronous_cycle_time has passed, this bit becomes 1. bit3 cycle timer over flow when the cycle_timer overflows, this bit becomes 1. bit2 local cycle event occurred when an local cycle event occurs, this bit becomes 1. bit1 cycle start packet lost when the cycle_start_packet does not exist over two local cycle events, this bit becomes 1. bit0 cyclestartpkt arbitration failed when a cycle_start_packet cannot be transmitted before the subactiongap after a local cycle event occurs, this bit becomes 1. this bit is enabled when cmstr = 1. address register name bit symbol r/w description h.rst s.rst b.rst 0x05 linkintstat0 7: unexpch r(w) 0: none 1: unknown expected channel 6: duplich r(w) 0: none 1: duplicatechanneldetected 5: isoarbfaild r(w) 0: none 1: iso arbtration failed 4: cyctoolong r(w) 0: none 1: iso arbitration failed 0x00 0x00 C 3: cycoverflw r(w) 0: none 1: cycle timer over fullow 2: cycevent r(w) 0: none 1: local cycle event occured 1: cyclost r(w) 0: none 1: cycle start packet lost 0: cycarbfail r(w) 0: none 1: cyclestartpkt arbtration fail
S1R72801F00A epson 47 address register name bit symbol r/w description h.rst s.rst b.rst 0x06 phyintstat 7: subgap r(w) 0: none 1: sub action gap detected 6: arbgap r(w) 0: none 1: arbtrationresetgapdetected 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: phy_int r(w) 0: none 1: phy interrupt detected 1: phywrdone r(w) 0: none 1: phy register write done 0: phyrddone r(w) 0: none 1: phy register read done address register name bit symbol r/w description h.rst s.rst b.rst 0x07 (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: phy interrupt status register the value of each bit of this register indicates the status of a corresponding interrupt source. if these bits become 1 when the associated bit of the phyintenb register is 1, this register asserts the interrupt signal to the cpu. the cpu reads this register after receiving the interrupt signal to locate an interrupt source. by writing the read value again, it clears these bits. bit 7 sub action gap detected when a transmit action gap is detected in the phy status of the phy/link interface, this bit becomes 1. bit6 arbitration reset gap detected when an arbitration reset gap is detected in the phy status of the phy/link interface, this bit becomes 1. bit5 reserved bit4 reserved bit3 reserved bit2 phy/link interface interrupt detected when a phy_interrupt is detected in the phy status of the phy/link interface, this bit becomes 1. this status indicates the phy is put under one of the following. 1) in most instances, a loop is created in the cable topology. 2) cable power is insufficient. 3) a bias change is detected. bit1 phy register write done when the write access of the phy register is complete, this bit becomes 1. bit0 phy register read done when read data is stored in the phyrdstat register at the time of read access of the phy register, this bit becomes 1.
S1R72801F00A 48 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x08 mainintenb 7: ensubintstat r/w 0: disable 1: enable 6: entxisocmp r/w 0: disable 1: enable 5: enrxdmacmp r/w 0: disable 1: enable 4: entxasycmp r/w 0: disable 1: enable 0x00 0x00 C 3: enhwsbp2cmp r/w 0: disable 1: enable 2: enide_dmacmp r/w 0: disable 1: enable 1: enide_intrq r/w 0: disable 1: enable 0: enbusreset r/w 0: disable 1: enable address register name bit symbol r/w description h.rst s.rst b.rst 0x09 subintenb 7: enselfiddone r/w 0: disable 1: enable 6: enselfiderr r/w 0: disable 1: enable 5: enhwsbp2err r/w 0: disable 1: enable 4: enhwsbp2brst r/w 0: disable 1: enable 0x00 0x00 C 3: enlinkintstat1 r/w 0: disable 1: enable 2: enlinkintstat0 r/w 0: disable 1: enable 1: enphyintstat r/w 0: disable 1: enable 0: endmaintstat r/w 0: disable 1: enable address register name bit symbol r/w description h.rst s.rst b.rst 0x0a (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: main interrupt enable flag register this register enables/disables an interrupt factor of the mainintstat register. setting the corresponding bit to 1 enables an interrupt to the cpu. sub-interrupt enable flag register this register enables/disables an interrupt factor of the subintstat register. setting the corresponding bit to 1 enables an interrupt to the cpu.
S1R72801F00A epson 49 address register name bit symbol r/w description h.rst s.rst b.rst 0x0b dmaintenb 7: 0: 1: 6: entxasyrtygo r/w 0: disable 1: enable 5: entxasybcsent r/w 0: disable 1: enable 4: enrxdmafaild r/w 0: disable 1: enable 0x00 0x00 C 3: entxasyfaild r/w 0: disable 1: enable 2: entxisofaild r/w 0: disable 1: enable 1: entxasybrabort r/w 0: disable 1: enable 0: entxasymiss r/w 0: disable 1: enable dma interrupt enable flag register this register enables/disables an interrupt factor of the dmaintstat register. setting the corresponding bit to 1 enables an interrupt to the cpu. address register name bit symbol r/w description h.rst s.rst b.rst 0x0c linkintenb1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: enrxontardy r/w 0: disable 1: enable 2: enrxhcrcerr r/w 0: disable 1: enable 1: enrxunktcode r/w 0: disable 1: enable 0: entxrtyexced r/w 0: disable 1: enable link core interrupt enable flag register 1 this register enables/disables an interrupt factor of the linkintstat1 register. setting the corresponding bit to 1 enables an interrupt to the cpu. address register name bit symbol r/w description h.rst s.rst b.rst 0x0d linkintenb0 7: enunexpch r/w 0: disable 1: enable 6: enduplich r/w 0: disable 1: enable 5: enisoarbfaild r/w 0: disable 1: enable 4: encyctoolong r/w 0: disable 1: enable 0x00 0x00 C 3: encycoverflw r/w 0: disable 1: enable 2: encycevent r/w 0: disable 1: enable 1: encyclost r/w 0: disable 1: enable 0: encycarbfail r/w 0: disable 1: enable link core interrupt enable flag register 0 this register enables/disables an interrupt factor of the linkintstat0 register. setting the corresponding bit to 1 enables an interrupt to the cpu.
S1R72801F00A 50 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x10 chipctl 7: suspend r/w 0: resume 1: suspend 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: ide_mdlrst w 0: none 1: ide_module reset 1: sendtardy r/w 0: none 1: send ack_tardy 0: softreset w 0: none 1: reset start chip control register the chip ctl register controls the internal circuit of a chip. bit7 suspend setting this bit to 1 stops the sclk supplied from the phy to this ic. at that time, the lps signal must be negated as well. when a linkon packet is received, the cpu asserts the xint. after asserting it, the firmware asserts the lps signal to the phy and resume it by the sclk supplied from the phy. at that time, this bit must be set to 0. bit6 reserved bit5 reserved bit4 reserved bit3 reserved bit2 ide_mdlrst setting this bit to 1 resets ide-related registers (0x60 - 0x7f) to restore them to the initial state. bit1 send ack_tardy enable makes setting to return an ack_tardy as a ack code when receiving an async packet. 0: usual ack code 1: ack_tardy bit0 soft reset setting this bit to 1 initializes the interiors of the circuit. after initializing it, it is restored to 0. address register name bit symbol r/w description h.rst s.rst b.rst 0x0e phyintenb 7: ensubgap r/w 0: disable 1: enable 6: enarbgap r/w 0: disable 1: enable 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: enphy_int r/w 0: disable 1: enable 1: enphywrdone r/w 0: disable 1: enable 0: enphyrddone r/w 0: disable 1: enable address register name bit symbol r/w description h.rst s.rst b.rst 0x0f (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: phy core interrupt enable flag register this register enables/disables an interrupt factor of the phyintstat register. setting the corresponding bit to 1 enables an interrupt to the cpu.
S1R72801F00A epson 51 address register name bit symbol r/w description h.rst s.rst b.rst 0x11 hw_revision 7: hw_revision[7] 6: hw_revision[6] 5: hw_revision[5] 4: hw_revision[4] r indicate hard ware revison number 0x03 0x03 0x03 3: hw_revision[3] 2: hw_revision[2] 1: hw_revision[1] 0: hw_revision[0] hardware revision register the hw_revision register indicates the revision number of a chip. address register name bit symbol r/w d escription h.rst s.rst b.rst 0x18 linkctl_h 7: passselfid 0: non passselfid 1: selfCid to dma fifo 6: passphypkt 0: non pass phy packet 1: phy pkt to dma fifo 5: passbrpkt 0: non pass busrst packet 1: busrst pkt to dma fifo 4: enposwb r/w 0: disable posted wb 1: enable posted wb 0x00 0x00 C 3: enposwq 0: disable poosted wq 1: enable posted wq 2: aphy 0: phy 1394.a uncorrespond 1: phy 1394.a correspond 1: enacc 0: ack acceleration disable 1: ack acceleration enable 0: cmstr 0: cycle master not capabl 1: cycle master capable link core control register higher rank this register controls the functions of the link core. bit7 pass self-id packet setting this bit to 1 captures a self-id packet received by the link core into the buffer. bit6 pass phy packet when requesting the phy register for a register write, this bit is set to 1. after the execution, this bit is cleared. bit5 pass busreset packet setting this bit to 1 captures a busreset packet received by the link core into the buffer. bit4 enable posted block write setting this bit to 1 enables the posted write function for a block write request. bit3 enable posted quadlet write setting this bit to 1 enables the posted write function for a quadlet write request. bit2 aphy indicates whether the phy conforms to 1394.a or not. 1: conforms to phy 1394.a 0: does not conform to phy 1394.a bit1 enable ack acceleration indicates the setting of ack acceleration. 1: ack acceleration enable 0: ack acceleration disable bit0 cmstr when the self node is cycle master capable and a root, this bit becomes 1. if the self node does not become a root in the self-id processing when this bit is set after the bus reset, this bit is cleared.
S1R72801F00A 52 epson link core control register lower rank this register controls the functions of the link core. bit7 enable link controls whether communications with other nodes are enabled. when this bit is 0, no response is given to a received packet. when it is 1, the transmission/reception of a packet becomes possible. even if you set the enlink to 1 when the lps bit is 0, it is ignored. before setting it to 1, set the lps bit to 1 and wait 10ms. bit6 reserved bit5 phy/link interface reset writing 1 to this bit resets the phy/link interface. after resetting it, this bit is automatically restored to 0. bit4 ignore broadcast packet setting this bit to 1 abandons a broadcast packet received by the link core. bit3 ignore broadcast packet data setting this bit to 1 abandons a broadcast data received by he link core. bit2 rx busy mode sets a busy type, the dual phase mode or single phase mode, for a received packet when returning a busy. when this is 1, an ack_busy_x is returned. when it is 0, an ack_busy_a or ack_busy_b is returned. bit1 dual phase retry enable controls whether the dual phase retry protocol is enabled. when this bit is 1, a retry processing is done until a time set on the retry limit register is exceeded. when it is 0, no retry is done. when the value of the retry limit register is 0, a retry processing is ignored. bit0 single phase retry enable controls whether the single phase retry protocol is enabled. when this bit is 1, a retry processing is done until the number set on the retry limit register is exceeded. when it is 0, a retry processing is disabled. when the value of the maxretry register is 0, a retry processing is ignored. address register name bit symbol r/w description h.rst s.rst b.rst 0x19 linkctl_l 7: enlink r/w 0: disable link 1: enable link C C 6: 0: 1: C C 5: plifrst w 0: none 1: reset phy/link i/f 0 C 4: ignrbchdr r/w 0: bc pkt to dma fifo 1: ignore bc packet 0x00 0 C 3: ignrbcdata r/w 0: bc data to dma fifo 1: ignore bc C data 0 C 2: rxbusymode r/w 0: dual 1: single 0 C 1: dualrtyenb r/w 0: dual retry disable 1: dual retry enable 0C 0: singlrtyenb r/w 0: single retry disable 1: single retry enable 0C address register name bit symbol r/w description h.rst s.rst b.rst 0x1a linkstart 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 C C 3: 0: 1: 2: id_valid r 0: phyid invalid 1: phyid valid 1: root r 0: self node =not root 1: self node =root 0: cablpwsts r 0: cable power status ng 1: cable power status ok link core status read register bit 7..3 reserved bit2 id_valid when this bit is set to 1, the physical_id of the nodeid register becomes valid, and when this bit is set to 0, the physical_id becomes invalid. bit1 root this bit is set to 1 when the self node comes to root in the self-id process after the bus is reset. bit 0 cable power status this bit indicates the status of cable power, which is updated in the phy status. 1 : cable power status ok 0 : cable power status ng
S1R72801F00A epson 53 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x1c retrylimit_h 7: seclimit[2] dual phase retry limit 6: seclimit[1] r/w second limit 5: seclimit[0] 4: cyclimt[12] 0x00 0x00 C 3: cyclimt[11] 2: cyclimt[10] 1: cyclimt[9] 0: cyclimt[8] 0x1d retrylimit_l 7: cyclimt[7] r/w cycle limit 6: cyclimt[6] 5: cyclimt[5] if (seclimit == 0 and cyclimit==0) 4: cyclimt[4] dual phase is ignore 0x00 0x00 C 3: cyclimt[3] 2: cyclimt[2] 1: cyclimt[1] 0: cyclimt[0] dual retry time set register (higher rank, lower rank) this register is used for the dual phase retry protocol to set a retransmit retry time limit when an async transmit packet is transmitted and a busy is returned. when this register is 0, the dual phase retry is ignored. 0x1c bit7..5 second_limit[2:0] set a dual phase retry time (unit: second). 0x1c, 0x1d cycle limit[12:0] sets a retry time at cycle limit [12:0] (unit: 125 m s). address register name bit symbol r/w d escription h.rst s.rst b.rst 0x1b prireqcnt 7: 0: 1: 6: 0: 1: 5: prireq[5] 4: prireq[4] 0x00 0x00 0x00 3: prireq[3] r/w maximum number of certain priority arb request 2: prireq[2] 1: prireq[1] 0: prireq[0] priority request count register this register shows registers in the pri-req field shown in the priority_budget(csr) register. this register can precede the priority request as often as it is set to prireq in a uniform section. but this register can only be set by the node suitable for the bus manager. bit7..6 reserved bit5..0 pri_req[9:0] this bit is for setting the value of pri_req designated by the bus manager. any value exceeding the value of pri_max to be packaged with the firmware cannot be set. the value is cleared to zero when a uniform section ends.
S1R72801F00A 54 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x1f irm_stat 7: noirm r 0: exist irm node 1: none irm node 6: wonirm r(w) 0: other node 1: self node 5: irmid[5] 4: irmid[4] physical id of irm node 0x3f C 0x3f 3: irmid[3] r no exist irm node then irmid=0x3f 2: irmid[2] 1: irmid[1] 0: irmid[0] address register name bit symbol r/w d escription h.rst s.rst b.rst 0x1e maxretry 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: maxrty[3] single phase retry limit 2: maxrty[2] r/w max retry count value 1: maxrty[1] if maxrty == 0, single phase retry is ignore 0: maxrty[0] single retry limit set register this register sets the number of retries of the single phase retry protocol. when its value is 0, the single phase retry is ignored. bit7..4 reserved bit3..0 single retry limit[3:0] sets the number of retries in the single phase at maxrtry[3:0] irm status register this irm status register controls detection of the isochronous resource manager. bit7 no irm sets whether an isochronous resource manager exists on the serial bus. 1 indicates the irm node does not exist and 0 indicates the irm node exists. bit6 wonirm sets whether the isochronous resource manager is self node or other node. 1 indicates it is the self node and 0 indicates it is other node. usually, this bit is read-only. when a valid irm is not detectable due to hardware bugs, however, the firmware sets this bit through a self-id packet or topology map. bit5..0 irm id[5:0] when the enlrmdetect bit is 1, the node id of the isochronous resource manager detected in the self-id period is set. when no node corresponding to the irm exists, it indicates the 0x3f value.
S1R72801F00A epson 55 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x20 node_ids_h 7: busid[9] 6: busid[8] 5: busid[7] serial bus id number 4: busid[6] single bus, bus id = 0x3ff 0xff C C 3: busid[5] r/w multiple bus, bus id is uniquely specifying 2: busid[4] 1: busid[3] 0: busid[2] 0x21 node_ids_l 7: busid[1] C 6: busid[0] C 5: phyid[5] 1 4: phyid[4] 0xff C 1 ultradmamode 3: phyid[3] r self node's physical id number 1 2: phyid[2] 1 1: phyid[1] 1 0: phyid[0] 1 node ids status register (higher rank, lower rank) this register indicates the bus id of topology connected through the serial bus. at the time of busreset, the busid does not change. when the self node is a bus manager, this register is writable. if you write when it is not a bus manager, the bus goes out of control. never write when it is not a bus manager. the phy id becomes a value of the 0x3f at the time of busreset and is automatically stored on completion of the self-id processing. 0x20, 0x21 .bit7..6 bus id these bits are areas to store the bus_id value of the serial bus. 0x21 bit5:0 phy id indicates the physical id of a node established by the phy in the self-id phase. address register name bit symbol r/w d escription h.rst s.rst b.rst 0x24 phyaccctl_h 7: rdreq r/w 0: normal 1: phy reg rd request 6: wrreq r/w 0: normal 1: phy reg wr request 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: reqadd[3] 2: reqadd[2] r/w phy register read/write request address 1: reqadd[1] 0: reqadd[0] phy register access control register (higher rank) bit7 phy register read request when requesting the phy register for a register read, this bit is set to 1. after the execution, it is automatically cleared. bit6 phy register write request when requesting the phy register for a register write, this bit is set to 1. after the execution, it is automatically cleared. bit5 reserved bit4 reserved bit3..0 phy access register set a register address to access the phy register.
S1R72801F00A 56 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x25 phyaccctl_l 7: wrdat[7] 6: wrdat[6] 5: wrdat[5] 4: wrdat[4] r/w phy register write data 0x00 0x00 C 3: wrdat[3] 2: wrdat[2] 1: wrdat[1] 0: wrdat[0] address register name bit symbol r/w d escription h.rst s.rst b.rst 0x27 phyrdstat_l 7: rddat[7] 6: rddat[6] 5: rddat[5] 4: rddat[4] r phy register read data 0x00 0x00 C 3: rddat[3] 2: rddat[2] 1: rddat[1] 0: rddat[0] phy register access control register (lower rank) bit7..0 phy write data set data to write to the phy register. phy register read status register (higher rank) bit7 reserved bit6 reserved bit5 reserved bit4 reserved bit3..0 phy read address indicate a register address indicated in the phy status. phy register read status register (lower rank) bit7..0 phy read data indicate register data indicated in the phy status. address register name bit symbol r/w d escription h.rst s.rst b.rst 0x26 phyrdstat_h 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rdadd[3] 2: rdadd[2] r phy register read address 1: rdadd[1] 0: rdadd[0]
S1R72801F00A epson 57 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x28 chnlindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: channel index[3] 2: channel index[2] r/w iso (async stream) channel index 1: channel index[1] 0: channel index[0] 0x29 chnlwindow 7: channel window[7] 6: channel window[6] 5: channel window[5] 4: channel window[4] r/w iso (async stream) 0x00 0x00 C 3: channel window[3] cahnnel window 2: channel window[2] 1: channel window[1] 0: channel window[0] iso-asyno stream channel index window register this register selects an iso channel and async stream channel. the channel available register is available when the isochronous resource manager is used. 0x28 channel index sets an index number to select a channel. 0x29 channel window indicates a window specified by the channel index. channelavailable this is a register to provide a channel number resource to be used when transferring isochronous and asynchronous stream. receivechannel this is a register to set an iso channel number to be received by this ic. chnlindex chnlwindow bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 channelavailableh0 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x01 channelavailableh1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x02 channelavailableh2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x03 channelavailableh3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x04 channelavailablel0 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x05 channelavailablel1 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x06 channelavailablel2 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x07 channelavailablel3 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 0x08 receivechannel0 ch00 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x09 receivechannel1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x0a receivechannel2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x0b receivechannel3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x0c receivechannel4 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x0d receivechannel5 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x0e receivechannel6 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x0f receivechannel7 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63
S1R72801F00A 58 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x2a cmprindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: compare index[3] 2: compare index[2] r/w compare address index 1: compare index[1] 0: compare index[0] 0x2b cmprwindow 7: compare window[7] 6: compare window[6] 5: compare window[5] 4: compare window[4] r/w compare address window 0x00 0x00 C 3: compare window[3] 2: compare window[2] 1: compare window[1] 0: compare window[0] compare offset address index window register this register sets a compare offset address. when the blkwrareaset bit is 1 and a blockwriterequest packet having an destination_offset address same as a value set to this register is received, the received data of payload is received by the rxstreamarea. 0x2a compare index this is a register to set an index number to select a channel. 0x2b compare window this is a register to view a window specified by the compare index. compare destination offset address when the blkwrareaset bit is 1 and a blockwriterequest packet having an destination_offset address same as a value set to this register is received, the received data of payload is received by the rxstreamarea. this address is valid when the blkwrareasel bit of the asydmactl register is 1. compare address index/window register chnlindex chnlwindow bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 comparedoffset0 (msb) 0x01 comparedoffset1 0x02 comparedoffset2 compare destination offset address[47:0] 0x03 comparedoffset3 0x04 comparedoffset4 0x05 comparedoffset5 (lsb) 0x06 (reserved) : (reserved) 0x0f (reserved)
S1R72801F00A epson 59 cycle time register each of cycsecond, cyccount, and cycoffset registers updates the timer by updating the current value of the cycle timer used for isochronous transfer. when the self node is a cycle master, set the value of each register in the cycle start packet. when the self node is not a cycle master, set the cycle_time_data of a received cycle start packet on each register. this register is enabled when linkctl(hi). discyctimer=0. reserve this register as a cycsecond(hi) for word access. cycle_time.second_count this bit field indicates an integer at the place of second of the cycle timer. it is enabled when the linkctl(h).discyctimer= 0 and the cycle second is incremented every time the cyclecount reaches 8000. when the cycle second exceeds 127, it is restored to 0. cycle_time.cycle_count when the self node is a cycle master and the discyctimer=0, it is incremented every time the cycle offset reached 3072. when the cycle count reaches 8000, it is restored to 0. cycle_time. cycle.offset when the self node is a cycle timer and the discyctimer=0, it is incremented in a cycle of 24.576mhz. when the cycle offset reaches 3072, it is restored to 0 and then the cycle count is incremented. address register name bit symbol r/w d escription h.rst s.rst b.rst 0x2c cycle_time_h 7: cycle second[6] 6: cycle second[5] 5: cycle second[4] 4: cycle second[3] r/w cycle_time.second_count 0x00 C C 3: cycle second[2] 2: cycle second[1] 1: cycle second[0] 0: cycle count[12] 0x2d cycle_time_mh 7: cycle count[11] 6: cycle count[10] 5: cycle count[9] 4: cycle count[8] 0x00 C C 3: cycle count[7] 2: cycle count[6] r/w cycle_time.cycle_count 1: cycle count[5] 0: cycle count[4] 0x2e cycle_time_ml 7: cycle count[3] 6: cycle count[2] 5: cycle count[1] 4: cycle count[0] 0x00 C C 3: cycle offset[11] 2: cycle offset[10] 1: cycle offset[9] 0: cycle offset8[] 0x2f cycle_time_l 7: cycle offset[7] 6: cycle offset[6] r/w cycle_time.cycle_offset 5: cycle offset[5] 4: cycle offset[4] 0x00 C C 3: cycle offset[3] 2: cycle offset[2] 1: cycle offset[1] 0: cycle offset[0]
S1R72801F00A 60 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x30 hwsbp2ctl 7: ptnotpresent r/w 0: present 1: not present 6: hosttodev r/w 0: host device 5: fromstream r/w 0: from pagetable 1: fromstream 4: 0: 1: 0x00 0x00 C 3: hwsbp2rst w 0: none 1: reset 2: hwsbp2rsum w 0: none 1: resume 1: hwsbp2pause w 0: none 1: pause 0: hwsbp2start w 0: none 1: start hardware sbp2 control register this register controls the sbp2 processing of this ic. bit7 ultradmamode ptnotpresent:0 (present) set => pagetable exists. ptnotpresent:1 (not present) set => pagetable does not exist. bit6 hosttodev hosttodev:0 (host<-device) set => transfers data from device to host. hosttodev:1 (host->device) set => transfers data from host to device. bit5 fromstream fromstream:0 (frompt) set => starts with the pagetable processing. fromstream:1 (fromstream) set => starts with the stream processing. bit4 reserved bit3 hwsbp2rst sbp2reset:1 (reset) set => resets the hwsbp2. if you read it, it indicates 0. bit2 hwsbp2rsum sbp2resume:1 (reset) set => resumes the hwsbp2 processing in pause. if you read it, it indicates 0. bit1 hwsbp2pause sbp2pause:1 (pause) set => pauses the hwsbp2 processing in execution. if you read it, it indicates 0. bit0 hwsbp2start sbp2start:1 (start) set => starts the hwsbp2 processing. if you read it, it indicates 0.
S1R72801F00A epson 61 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x31 hwsbp2stat 7: fwpause r 0: not firmware pause 1: firmwre pause 6: errpause r 0: not error pause 1: error pause 5: 0: 1: 4: waitplready r 0: not ready 1: ready 0x00 0x00 C 3: hwsbp2exec r 0: stop 1: execute 2: ptaskexec r 0: stop 1: execute 1: sttaskexec r 0: stop 1: execute 0: tranexec r 0: stop 1: execute hardware sbp2 status read register this register indicates the execution condition of the hardware sbp2. bit7 f/w pause when the firmware writes 1 at the hwsbp2ctl. hwsbp2pause bit during the execution of the hwsbp2pause:1 (pause) hwsbp2, this bit becomes 1. when the firmware writes 1 at the hwsbp2ctl.hwsbp2rsum bit or resets it, it is cleared. writing to this bit is ignored. bit6 error pause when firmware enters the pause state without writing 1 at the hwsbp2ctl.hwsbp2pause bit during the execution of the hwsbp2pause:1 (pause) hwsbp2, this bit becomes 1. it is cleared at the time of reset. writing to this bit is ignored. bit5 reserved bit4 wait payload ready ? waitplready:0 (not ready) => payload domain not ready ? waitplready:1 (ready) => payload domain ready when the ide interface has a problem, the payload may not be ready. at that time, perform a recovery processing by the firmware. bit3 hwsbp2exec ? hwsbp2exec:0 (stop) => indicates the hwsbp2 processing is completed. ? hwsbp2exec:1 (execute) => indicates the hwsbp2 processing is in execution. it is cleared at the time of reset. writing to this bit is ignored.. bit2 pagetaskexec ? pagetaskexec:0 (stop) => indicates a pagetask is completed. ? pagetaskexec:1 (execute) => indicates a pagetask is in execution. it is cleared at the time of reset. writing to this bit is ignored.. bit1 streamtaskexec ? streamtaskexec:0 (stop) => indicates a streamtask is completed. ? streamtaskexec:1 (execute) => indicates a streamtask is in execution. it is cleared at the time of reset. writing to this bit is ignored.. bit0 tranexec. ? tranexec:0 (stop) => indicates a transaction is completed. ? tranexec:1 (execute) => indicates a transaction is in execution. it is cleared at the time of reset. writing to this bit is ignored..
S1R72801F00A 62 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x32 hwsbp2intstat 7: splittimeout r(w) 0: none 1: splittimeout 6: txackedillegal r(w) 0: none 1: txackedillegal 5: txackmiss r(w) 0: none 1: txasymiss 4: brabort r(w) 0: none 1: brabort 0x00 0x00 C 3: 0: 1: 2: rxnotrespcmp r(w) 0: none 1: rxnotrespcmp 1: rxbroadcast r(w) 0: none 1: rxbroadcast 0: rxackdataerr r(w) 0: none 1: rxackdataerr hardware sbp2 interrupt status register this register indicates error information when an error arises in execution of the hardware sbp2 processing. at the same time, it asserts the hwsbp2err bit of the subintstat register. when clearing it, write 1 to a bit to clear. this register is automatically cleared when setting hwsbp2ctl.hwsbp2start or the hwsbp2ctl. hwsbp2rst. bit7 split timeout ? splittimeout:1 => during the hwsbp2 processing, an split timeout error arose. bit6 tx acked illegal txackedillegal:1 => though a transmission was completed, a response other than ack_pending was given to a blkrdreq and a response other than ack_completed was given to a blkwrreq. bit5 tx ack miss ? txasymiss:1 => though a transmission was completed, no ack was returned. bit4 brabort ? when the hwsbp2ctl.hwsbp2start bit is set to 1 or hwsbp2ctl.resume bit is set to 1 during the busreset period, this bit becomes 1, bit3 reserved bit2 rxnotrespcmp ? rxnotrespcmp:1 => though a response packet receive was completed, its code was other than resp_complete. bit1 rxbroadcast ? rxbroadcast:1 => though a response packet receive was completed, it was a broadcast packet. bit0 rxackdataerror ? rxackdataerr:1 => though a response packet was received, it was a datacrcerror. it does not assert the interrupt signal sbp2err. it is automatically cleared on completion of the transaction.
S1R72801F00A epson 63 address register name bit symbol r/w description h.rst s.rst b.rst 0x33 hwsbp2index 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: hwsbp2 index[3] 2: hwsbp2 index[2] r/w hwsbp2 index 1: hwsbp2 index[1] 0: hwsbp2 index[0] 0x34 hwsbp2window_h 7: hwsbp2 window [15] 6: hwsbp2 window [14] 5: hwsbp2 window [13] 4: hwsbp2 window [12] 0x00 0x00 C 3: hwsbp2 window [11] 2: hwsbp2 window [10] 1: hwsbp2 window[9] 0: hwsbp2 window[8] r/w hwsbp2 window 0x35 hwsbp2window_l 7: hwsbp2 window[7] 6: hwsbp2 window[6] 5: hwsbp2 window[5] 4: hwsbp2 window[4] 0x00 0x00 C 3: hwsbp2 window[3] 2: hwsbp2 window[2] 1: hwsbp2 window[1] 0: hwsbp2 window[0] hardware sbp2 index window register this register functions as an index register and window register to set a register to use for the hwsbp2 processing. hwsbp2index this register sets an index number to select a channel. hwsbp2window this register indicates a window specified by the hwsbp2index.
S1R72801F00A 64 epson h/w sbp2 index chnnel/window register sbp2index sbp2window_h/l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 pageboundary pageboundary[2:0] pageelementnunber pageelementnumber[4:0] 0x01 pgelmentremain_h (msb) page element remain length (bytes) pgelmentremain_l (lsb) 0x02 speedcode speedcode[2:0] maxpayload maxpayload[3:0] 0x03 destinationid_h (msb) destinationid_l destination_id value (lsb) 0x04 splittime_h second[2:0] cycle count[12:8] splittime_l cycle count[7:0] 0x05 (reserved) : (reserved) 0x0f (reserved) pageboundary set a value of page boundary to use for the hwsbp2. the actual page boundary is as follows. pageboundary =2 (pageboundary +8) bytes pageelementnumber sets a page element number with which the hwsbp2 starts a processing. when the hwsbp2ctl.ptpresent:1, set a value equal to or less. than 0x17 when the hwsbp2ctl.ptpresent:0, set a value equal to or less than 0x02. if you read it, the page element number currently in process is indicated. pgelementremain indicates the number of remaining data bytes of the page element currently being processed by the hwsbp2. this register is read-only. speedcode sets the speed code of 1394 bus to be used for data transfer by the hwsbp2. speedcode:0 100mbps speedcode:1 200mbps speedcode:2 400mbps speedcode:3 reserved maxpayload sets the max. payload value to be used by the hwsbp2. the actual payload size is as follows. payload = 2 (maxpayload+2) bytes since the max. payload size transferable at 400mbps is 2048 bytes, set 9 or less for this register. destination_id this is a register to set a transmit destination of the hwsbp2. set a bus id (10 bits) and node id (6 bits). splittime set a split timeout time of a transaction of the hwsbp2. splittime.second: set a value in second. splittime.cyclecount: set a value in 125 m s. (set range: 0 to 0x1f3f) setting of a value exceeding 0x1f3f is not possible.
S1R72801F00A epson 65 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x36 payloadsize_h 7: 6: 5: 4: 0x00 0x00 C 3: payload size[11] set payload size (bytes) 2: payload size[10] if (hwsbp2ctl.hwsbp2exec ==0) { 1: payload size[9] write is valid. 0: payload size[8] r/w } else { 0x37 payloadsize_l 7: payload size[7] write is invalid. 6: payload size[6] } 5: payload size[5] 4: payload size[4] 0x00 0x00 C 3: payload size[3] 2: payload size[2] 1: payload size[1] 0: payload size[0] hardware sbp2 payload size set register set this register when the firmware handles data to a streamarea to be used by the hwsbp2. when the hwsbp2stat.exec.:1" (in execution of hwsbp2), writing to this register is ignored. when the rxstreamarea receives data the equivalent of this size, the bufmoniter.rxpayldrdy bit becomes 1. if free space the equivalent of a size set here exists in the txstreamarea, the bufmoniter. txpayldrdy bit becomes 1. payload size [11:0] set a payload size to use for data transfer in byte. the settable size is 2 ^n (n:2 to 11) bytes. hardware page table size set register the write and read of this register have different meanings depending on whether a pagetable is present (setting of hwsbp2ctl.ptnotpresent bit). ? when a pagetable is present write: set a pagetable size in byte. (the number of pages x 8 bytes) read: indicates the remaining pagetable size. ? when a pagetable is not present write: set a data length. read: indicates a new pagetable size based on the written data size. (the number of pages x 8 bytes) when it is not written, zero can be read if the hwsbp2 correctly finishes. the remaining table size can be read when it is in execution or it finishes incorrectly. address register name bit symbol r/w d escription h.rst s.rst b.rst 0x38 pagetablesize_h 7: page table size[15] 6: page table size[14] 5: page table size[13] 4: page table size[12] if (hwsbp2ctl.ptnotpresent == 0) { 0x00 0x00 C 3: page table size[11] write:set pageelement *8 (bytes) 2: page table size[10] read :indicate page table size 1: page table size[9] } else { 0: page table size[8] r/w write:set data length (bytes) 0x39 pagetablesize_l 7: page table size[7] read : indicate create pageelement *8 (bytes) 6: page table size[6] } 5: page table size[5] 4: page table size[4] 0x00 0x00 C 3: page table size[3] 2: page table size[2] 1: page table size[1] 0: page table size[0]
S1R72801F00A 66 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x3a pagetableadrs0 7: ptadress[47] 6: ptadress[46] 5: ptadress[45] 4: ptadress[44] 0x00 0x00 C 3: ptadress[43] 2: ptadress[42] 1: ptadress[41] 0: ptadress[40] 0x3b pagetableadrs1 7: ptadress[39] 6: ptadress[38] 5: ptadress[37] 4: ptadress[36] 0x00 0x00 C 3: ptadress[35] 2: ptadress[34] 1: ptadress[33] 0: ptadress[32] 0x3c pagetableadrs2 7: ptadress[31] 6: ptadress[30] 5: ptadress[29] 4: ptadress[28] 0x00 0x00 C 3: ptadress[27] 2: ptadress[26] 1: ptadress[25] 0: ptadress[24] r/w write: set pagetable offset address 0x3d paqetableadrs3 7: ptadress[23] read: indicate nextpagetable offset address 6: ptadress[22] 5: ptadress[21] 4: ptadress[20] 0x00 0x00 C 3: ptadress[19] 2: ptadress[18] 1: ptadress[17] 0: ptadress[16] 0x3e pagetableadrs4 7: ptadress[15] 6: ptadress[14] 5: ptadress[13] 4: ptadress[12] 0x00 0x00 C 3: ptadress[11] 2: ptadress[10] 1: ptadress[9] 0: ptadress[8] 0x3f pagetableadrs5 7: ptadress[7] 6: ptadress[6] 5: ptadress[5] 4: ptadress[4] 0x00 0x00 C 3: ptadress[3] 2: ptadress[2] 1: ptadress[1] 0: ptadress[0] hardware sbp2 page table address set register this register specifies an address specified by the orb of the sbp2. it is automatically updated in execution of the hwsbp2. page table offset address write: sets a destination_offset_address accessed by the hwsbp2. it is ignored in execution of the hwsbp2. read: indicates the pagetable address following one being processed by the hwsbp2.
S1R72801F00A epson 67 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x40 linkrxhdrptr_h 7: write is ignore 6: read is always zero 5: 4: lrhp[12] 0x00 0x00 C 3: lrhp[11] 2: lrhp[10] 1: lrhp[9] r/w current received packet header area pointer 0: lrhp[8] 0x41 linkrxhdrptr_l 7: lrhp[7] 6: lrhp[6] 5: lrhp[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero ultradmamode 1: 0: receive header link pointer register this receive header link pointer register indicates the starting address of the latest receive packet in the rxheaderarea. since the buffer pointer is given in 8quadlet unit, the lower order 5 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes-lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.) receive o rb data link pointer register this receive orb data link pointer register indicates the starting address of the latest receive orb data in the rxorbdataarea. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.) address register name bit symbol r/w d escription h.rst s.rst b.rst 0x42 linkrxorbptr_h 7: write is ignore 6: read is always zero 5: 4: pop[12] 0x00 0x00 C 3: pop[11] 2: pop[10] 1: pop[9] 0: pop[8] 0x43 linkrxorbptr_l 7: pop[7] r/w c urrent received packet orb data area pointer 6: pop[6] 5: pop[5] 4: pop[4] 0x00 0x00 C 3: pop[3] 2: pop[2] 1: write is ignore 0: read is always zero
S1R72801F00A 68 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x44 linkrxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: psp[12] 0x00 0x00 C 3: psp[11] 2: psp[10] 1: psp[9] 0: psp[8] 0x45 linkrxstreamptr_l 7: psp[7] r/w current received packet stream data area pointer 6: psp[6] 5: psp[5] 4: psp[4] 0x00 0x00 C 3: psp[3] 2: psp[2] 1: write is ignore 0: read is always zero address register name bit symbol r/w d escription h.rst s.rst b.rst 0x46 linktxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: ptdp[12] 0x00 0x00 3: ptdp[11] 2: ptdp[10] 1: ptdp[9] 0: ptdp[8] 0x47 linktxstreamptr_l 7: ptdp[7] r current transmit packet data area pointer 6: ptdp[6] 5: ptdp[5] 4: ptdp[4] 0x00 0x00 3: ptdp[3] 2: ptdp[2] 1: write is ignore 0: read is always zero receive stream data link pointer register this receive stream data link pointer register indicates the starting address of the latest received stream data in the rxstreamdataarea. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.) transmit stream data link pointer register this transmit stream data link pointer register indicates the starting address of unused area in the rxstreamarea. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. this register is read-only. writing is ignored.
S1R72801F00A epson 69 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x4a usedrxorbptr_h 7: write is ignore 6: read is always zero 5: 4: uop[12] 0x00 0x00 C 3: uop[11] 2: uop[10] 1: uop[9] 0: uop[8] 0x4b usedrxorbptr_l 7: uop[7] r/w received packet orb data area used pointer 6: uop[6] 5: uop[5] 4: uop[4] 0x00 0x00 C 3: uop[3] 2: uop[2] 1: write is ignore 0: read is always zero address register name bit symbol r/w d escription h.rst s.rst b.rst 0x48 usedrxhdrptr_h 7: write is ignore 6: read always zero 5: 4: urhp[12] 0x00 0x00 C 3: urhp[11] 2: urhp[10] 1: urhp[9] r/w received packet header area used pointer 0: urhp[8] 0x49 usedrxhdrptr_l 7: urhp[7] 6: urhp[6] 5: urhp[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero 1: 0: used receive header pointer register this used receive header pointer register indicates the starting address of used header of a receive packet in the rxhdrarea. since the buffer pointer is in 8quadlet unit, the lower order 5 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.) used receive orb data pointer register this used receive orb data pointer register indicates the starting address of used orb data of receive packet in the rxorbarea. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.)
S1R72801F00A 70 epson address register name bit symbol r/w d escription h.rst s.rst b.rst 0x4e ide_txstreamptr_h 7: write is ignore 6: read is always zero 5: 4: itsp[12] 0x00 0x00 C 3: itsp[11] 2: itsp[10] 1: itsp[9] 0: itsp[8] 0x4f ide_txstreamptr_l 7: itsp[7] r/w transmit packet stream data area ide pointer 6: itsp[6] 5: itsp[5] 4: itsp[4] 0x00 0x00 C 3: itsp[3] 2: itsp[2] 1: write is ignore 0: read is always zero address register name bit symbol r/w d escription h.rst s.rst b.rst 0x4c ide_rxstreamptr_h 7: write is ignore 6: read is always zero 5: 4: irsp[12] 0x00 0x00 C 3: irsp[11] 2: irsp[10] 1: irsp[9] 0: irsp[8] 0x4d ide_rxstreamptr_l 7: irsp[7] r/w received packet stream data area ide pointer 6: irsp[6] 5: irsp[5] 4: irsp[4] 0x00 0x00 C 3: irsp[3] 2: irsp[2] 1: write is ignore 0: read is always zero receive stream data ide pointer register this receive stream data ide pointer register indicates the starting address of received stream data in the rxstreamarea that is to be transmitted to the ide side but not yet transmitted. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.) transmit stream data ide pointer register this transmit stream data ide pointer register indicates the starting address of stream data in the rxstreamarea to be stored following the data that was transmitted from the ide to the sram. since the buffer pointer is in quadlet unit, the lower order 2 bits are always 0. also, since the buffer size is 2 kbytes, the higher order 3 bits are always 0. reading the higher order bytes holds the lower order bytes. when writing to this register, write the higher order bytes and lower order bytes in order. (with timing of writing to the lower order bytes, the register is updated.)
S1R72801F00A epson 71 address register name bit symbol r/w d escription h.rst s.rst b.rst 0x50 bufcontrol 7: txstreamclr w 0: none affect 1: tx stream data clear 6: rxstreamclr w 0: none affect 1: rx stream data clear 5: rxorbclr w 0: none affect 1: rx orb dat clear 4: rxhdrclr w 0: none affect 1: rx header clear 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: updlinktxstrm w 0: none affect 1: update link tx stream ptr buffer control register this buffer control register restores each pointer of the txstreamarea, rxstreamarea, rxorbarea, and rxheaderarea to the initial set pointer address. it also controls updates of the linktxstreamptr. this register is read-only. if you read it, it always indicates zero. bit7 tx stream clear writing 1 to this bit changes the values of linktxstreamptr and ide_txstreamptr to ones set by the txstreamareastart register. bit6 rx stream clear writing 1 to this bit changes the values of linkrxstreamptr and ide_rxstreamptr to ones set by the rxstreamareastart register. bit5 rx orb clear writing 1 to this bit changes the values of linkrxorbptr and ide_rxorbptr to ones set by the rxorbareastart register. bit4 rx header clear writing 1 to this bit changes the values of linkrxhdrptr and usedrxhdrptr to the value of 0x0100. bit3::1 reserved bit0 update linktxstreamptr writing 1 to this bit updates the value of linktxstreamptr to the latest value. when the firmware transmits data, this bit confirms that the transmit is normally completed as an error recovery to update the linktxstreamptr. do not use this bit in execution of the hwsbp2.
S1R72801F00A 72 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x51 bufmonitor 7: rxpayldrdy r 0: rx payld capa not ready 1: rx payload capa ready 6: txpayldrdy r 0: tx payld capa not ready 1: tx payload capa ready 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rxhdrremain r 0: rx header area empty 1: rx header not empty 2: rxorbfull r 0: rx orb area not full 1: rx orb data area full 1: rxstreamfull r 0: rx stream area not full 1: rx stream data area full 0: rxhdrfull r 0: rx header area not full 1: rx header area full buffer monitor register this buffer monitor register indicates each buffer area status. this register is read-only. writing to this register is ignored.. bit7 rx payload ready when a free space the equivalent of the size set by the pyloadsize register exists in the rxstreamarea, this bit becomes 1. when not, this bit becomes 0. bit6 tx payload ready when transmit data the equivalent of the size set by the payloadsize register is accumulated in the rxstreamarea, this bit becomes 1. when not, this bit becomes 0. bit5::4 reserved bit3 received header remain when an unused packet header exists in the header area of a receive packet, this bit becomes 1. when the firmware rewrites the usedrxhdrptr to one same as linkrxhdrptr or when you write 1 to the bufcontrol.rxhdrctr bit, this bit becomes 0. bit2 received orb data full when the orb buffer area of receive packet data is full of received data, this bit becomes 1. the firmware must turn on rxdmactl.forcebusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. when the receive buffer area is freed, the rxdmactl.forcebusy is cleared. bit1 received stream data full when the stream buffer area of receive packet data is full of received data, this bit becomes 1. the firmware must turn on the rxdmactl.forcebusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. when the receive buffer area is freed, the rxdmactl.forcebusy is cleared. bit0 received header full when the header area of receive packet data is full, this bit becomes 1. the firmware must turn on the rxdmactl.forcebusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. when the receive buffer area is freed, the rxdmactl.forcebusy is cleared.
S1R72801F00A epson 73 address register name bit symbol r/w description h.rst s.rst b.rst 0x52 asydmactl 7: asychnlsel r/w 0: asytxpkthdr0 1: asytxpkthdr1 6: 0: 1: 5: 0: 1: 4: blkwrareasel r/w 0: rx orb area 1: rx stream area 0x00 0x00 C 3: asyfifoepty r 0: asyfifo empty 1: non empty 2: asyfifoclr w 0: normal 1: asyfifo clear 1: asytxmon r 0: async tx stop 1: async tx run 0: asystart w 0: normal 1: async start async txdma control register bit7 async transmit packet header channel select selects the header area of an async transmit packet from dma. you transmit send a transmit packet from the selected area. this bit selects 0: asynctxpkthdr0 or 1: asynctxpkthdr1. since the asynctxpkthdr1 area overlaps the isotxpkthdr area, however, the firmware must decide how to use this area. bit6 reserved bit5 reserved bit4 block write request packet data area select can divide the store area of the block write request packet data between the rxorbarea and rxstreamarea. o:rxorbarea 1:rxstreamarea bit3 async fifo empty when the dma-fifo for async is empty, this bit becomes 0. when it is not empty, it is 1. this bit is read- only and writing to this bit is ignored. bit2 async fifo clear clears the dma-fifo for async. writing 1 to this bit clears the fifo. after clearing it, this bit is automatically restored to 0. bit1 async transmit monitor indicates the transmit status of async. 1 indicates that an async packet is in transmission and 0 indicates that no async packet is in transmission. this bit is read-only and writing to this bit is ignored. bit0 async transmit start transmits an async packet. writing 1 to this bit starts to transmit an async packet. on completion of the transmission, it is automatically restored to 0. if you read this bit, it always indicates 0 regardless of presence/absence of transmit.
S1R72801F00A 74 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x53 isodmactl 7: isochnlsel r/w 0: isotxpkthdr0 1: isotxpkthdr1 6: 0: 1: 5: 0: 1: 4: seltxptr r/w 0: async tx pointer select 1: iso tx pointer select 0x00 0x00 C 3: isofifoepty r 0: isofifo empty 1: non empty 2: isofifoclr w 0: normal 1: isofifo clear 1: isotxmon r 0: iso tx stop 1: iso tx run 0: isostart w 0: normal 1: start iso txdma control register bit7 iso transmit packet header channel select selects the header area of an iso transmit packet from dma. you can transmit a transmit packet from the selected area. this bit selects 0: isotxpkthdr0 or 1: isotxpkthdr1. since the isoasynctxpkthdr0 and isoasynctxpkthdr1 areas overlap the asynctxpkthdr1 area, however, the firmware must decide how to use this area. bit6..5 reserved bit4 select transmit pointer can switch the address pointed by the posttxdataptr of a transmit packet to one for async or iso. the posttxdata ptr indicates a pointer of current transmit address; 0 indicates it is for async and 1 indicates it is for iso. bit3 iso fifo empty when the dma-fifo for iso is empty, this bit becomes 0. when it is not empty, it is 1. this bit is read- only and writing to this bit is ignored. bit2 iso fifo clear clears the dma-fifo for iso. writing 1 to this bit clears the fifo. after clearing it, this bit is automatically restored to 0. bit1 iso transmit monitor indicates the transmit status of iso. 1 indicates that an iso packet is in transmission and 0 indicates that no iso packet is in transmission. this bit is read-only and writing to this bit is ignored. bit0 iso transmit start transmits an iso packet. writing 1 to this bit starts to transmit an iso packet. on completion of the transmission, it is automatically restored to 0. if you read this bit, it always indicates 0 regardless of presence/absence of transmit.
S1R72801F00A epson 75 address register name bit symbol r/w description h.rst s.rst b.rst 0x54 rxdmactl 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: rxfifoepty r 0: rx fifo empty 1: non empty 2: rxfifoclr w 0: normal 1: rx fifo clear 1: rxmon r 0: rx stop 1: rx run 0: forcebusy r/w 0: normal 1: busy rx dma control register bit7..4 reserved bit3 receive fifo empty when the dma-fifo for reception is empty, this bit becomes 0. when it is not empty, it is 1. this bit is read-only and writing to this bit is ignored. bit2 receive fifo clear clears the dma-fifo for reception. writing 1 to this bit clears the fifo. after clearing it, this bit is automatically restored to 0. bit1 reception monitor indicates the receive status of iso. 1 indicates that a receive packet is in reception and 0 indicates that no receive packet is in reception. this bit is read-only and writing to this bit is ignored. bit0 force busy setting this bit to 1 can forcedly return an ack_busy to a receive packet. before performing the rxdata clear or rxhdrclear, be sure to set this bit. if you set this bit during receiving a packet, the packet operates to complete the reception regardless of to what extent the packet has been received. it means that a rxdmacmp interrupt occurs if this packet has been correctly received. the ack_busy is continuously returned to the subsequent receive packets.
S1R72801F00A 76 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x55 areaindex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: memmapindex[3] 2: memmapindex[2] r/w memory map area index 1: memmapindex[1] 0: memmapindex[0] 0x56 areawindow_h 7: memmapwindow[15] 6: memmapwindow[14] 5: memmapwindow[13] 4: memmapwindow[12] 0x00 0x00 C 3: memmapwindow[11] 2: memmapwindow[10] 1: memmapwindow[9] 0: memmapwindow[8] r/w memory map area window 0x57 areawindow_l 7: memmapwindow[7] 6: memmapwindow[6] 5: memmapwindow[5] 4: memmapwindow[4] 0x00 0x00 C 3: memmapwindow[3] 2: memmapwindow[2] 1: memmapwindow[1] 0: memmapwindow[0] memory map area set index window register this register is an index register and window register to set each area of a memory map. memmapindex sets an index number to select a register to set the starting address of each area of a memory map. memmapwindow indicates a window specified by the memmapwindow.
S1R72801F00A epson 77 rxorbareastart this register sets the starting address of a receive orb data area. txheaderareastart this register sets the starting address of a transmit header area. txstreamareastart this register sets the starting address of a transmit stream data area. txstreamareaend this register sets the ending address of a transmit stream data area. the actual data store area is up to immediately before this specified address. rxstreamareastart this register sets the starting address of a receive stream data area. bus reset header pointer register this bus reset header pointer register holds the value of a postrxhdrptr when a bus reset occurs. when several bus resets occur, it is updated to the latest postrxhdrptr. this register is read-only and writing to this register is ignored. address register name bit symbol r/w description h.rst s.rst b.rst 0x58 brsthdrptr_h 7: write is ignore 6: read is always zero 5: 4: busresetptr[12] 0x00 0x00 C 3: busresetptr[11] 2: busresetptr[10] bus reset header area pointer 1: busresetptr[9] r this register indicates address 0: busresetptr[8] in rx header area 0x59 brsthdrptr_l 7: busresetptr[7] when busrest detected. 6: busresetptr[6] 5: busresetptr[5] 4: 0x00 0x00 C 3: write is ignore 2: read is always zero 1: 0: memory map area index/window register areaindex areawindow_h/l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 rxorbareastart_h (msb) rxorbareastart[12:8] rxorbareastart_l rxorbareastart[7:2] (lsb) 0x01 txhdrareastart_h (msb) txhdrareastart[12:8] txhdrareastart_l txhdrareastart[7:2] (lsb) 0x02 txstreamareastart_h (msb) txstreamareastart[12:8] txstreamareastart_l txstreamareastart[7:2] (lsb) 0x03 txstreamareaend_h (msb) txstreamareaend[12:8] txstreamareaend_l txstreamareaend[7:2] (lsb) 0x04 rxstreamareastart_h (msb) rxstreamareastart[12:8] rxstreamareastart_l rxstreamareastart[7:2] (lsb) 0x05 (reserved) : (reserved) 0x0f (reserved)
S1R72801F00A 78 epson bus reset orb pointer register this bus reset header pointer register holds the value of a postrxorbptr when a bus reset occurs. when several bus resets occur, it is updated to the latest postrxorbptr. this register is read-only and writing to this register is ignored. address register name bit symbol r/w description h.rst s.rst b.rst 0x5a brstorbptr_h 7: write is ignore 6: read is always zero 5: 4: busrstorbptr[12] 0x00 0x00 C 3: busrstorbptr[11] 2: busrstorbptr[10] 1: busrstorbptr[9] 0: busrstorbptr[8] bus reset orb-data area pointer 0x5b brstorbptr_l 7: busrstorbptr[7] r this register indicates address 6: busrstorbptr[6] in rx orb data area 5: busrstorbptr[5] when busrest detected. 4: busrstorbptr[4] 0x00 0x00 C 3: busrstorbptr[3] 2: busrstorbptr[2] 1: write is ignore 0: read is always zero address register name bit symbol r/w description h.rst s.rst b.rst 0x5e maintctl_h 7: e_hcrc r/w 0: 1: add header crc error 6: e_dcrc r/w 0: 1: add data crc error 5: no_pkt r/w 0: 1: no transmit next packet 4: f_ack r/w 0: 1: tx optional ackcode 0x00 0x00 C 3: n_ack r/w 0: 1: no transmit ackpacket 2: 0: 1: 1: 0: 1: 0: 0: 1: maintenance control register this maintenance control register enables intentional generation of a serial bus error. bit7 error header crc writing 1 to this bit sets an invalid value for the header crc of a transmit packet to be generated next. after transmitting it, this bit is cleared to 0. bit6 error data crc writing 1 to this bit sets an invalid value for the data crc of a transmit packet to be generated next. after transmitting it, this bit is cleared to 0. bit5 no packet writing 1 to this bit abandons a transmit packet to be generated next. immediately after abandoning it, this bit is cleared. bit4 f_ack writing 1 to this bit transmits the value in the mainctl(lo).ack register to the ack packet to be generated next. immediately after transmitting it, this bit is cleared to 0. bit3 no_ack writing 1 to this bit abandons the ack packet to be generated next without transmitting it. immediately after abandoning it, this bit is cleared to 0. bit2..0 reserved
S1R72801F00A epson 79 address register name bit symbol r/w description h.rst s.rst b.rst 0x5f maintctl_l 7: ack[7] 6: ack[6] 5: ack[5] 4: ack[4] r/w optional ackcode 0x00 0x00 C 3: ack[3] 2: ack[2] 1: ack[1] 0: ack[0] maintenance control register when the f_ack bit is 1, this register is enabled. when the f_ack bit is set, an ack_code (ack[7::4]) and ack_parity(ack[3::0]) specified on this register are transmitted. bit7..4 ack code set an arbitrary ack code. bit3..0 ack_parity set a parity bit for the ack_code. address register name bit symbol r/w description h.rst s.rst b.rst 0x60 ide_config0 7: ultradmamode 0: dma mode 1: ultra dma mode 6: dmamode 0: pio mode 1: dma mode 5: actport 0: none 1: active 4: ide_slave r/w 0: master 1: slave 0x00 0x00 C 3: dmarq_level 0: positive logic 1: negative logic 2: swap 0: nomal 1: swap ide port hi & lo 1: 0: 1: 0: 0: 1: ide configuration register this register sets the mode of operation of the ide interface of this ic. bit7 ultradmamode when bit6:dmamode is 1 and bit 7:ultra dma mode is 1, this bit sets the dma transfer mode at ultra- dma. when bit6:dmamode is 0, the setting of this bit is invalid. bit6 dmamode sets the ide interface transfer mode at dma or pio. dmamode:1 dma mode dmamode:0 pio mode bit5 activate ide port the ide interface is in all-pin input mode after a reset. by setting this bit at 1, it is activated. bit4 ide port slave sets the mode of operation of the ide interface. when using the ide interface in ide compatible mode, set 1. in the master mode, the dma bit at bit 6 is reflected. ide_slave:1 slave mode (hdmacq is output and xhdmack/xhior/xhiow is input.) ide_slave:0 master mode (hdmacq is input and xhdmack/xhior/xhiow is output.) bit3 dmarq_level decides the level of operation of the hdmarq signal. set 0 when using the ide interface in ide bus compatible mode. dmarq_level:1 negative logic dmarq_level:0 positive logic bit2 swap swaps the higher order 8 bits and lower order 8 bits when using the interface at 16 bits width. the access order to an address of 0x70 of the ide-cso register is reversed. swap:1 transfers the higher order 8 bit data first. swap:0 transfers the lower order 8 bit data first. bit1::0 reserved
S1R72801F00A 80 epson ide configuration register this register sets the mode of operation of the ide interface of this ic. bit7 ide_reset writing 1 to this bit asserts the reset signal to the ide interface for 50 m s. during asserting the xhreset, this bit reads 1. if you reset it during the assertion, the xhreset is output for 50 m s from that time. bit6::0 reserved address register name bit symbol r/w description h.rst s.rst b.rst 0x62 ide_regacccyc 7: assert pulse[3] 6: assert pulse[2] r/w ide register access strobe signal assert pulse 5: assert pulse[1] width minimum value 4: assert pulse[0] 0x00 0x00 C 3: negate pulse[3] 2: negate pulse[2] r/w ide register access strobe signal negate pulse 1: negate pulse[1] width minimum value 0: negate pulse[0] ide register access cycle register this register sets a transfer mode when accessing the register area of the ide interface. it is enabled for an access to 0x70 to 0x7f of the ide-cs0/cs1 register. bit7::4 assert pulse decides the minimum value of the assert period of the strobe signal when accessing the register area of the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. bit3::0 negate pulse decides the minimum value of the negate period of the strobe signal when accessing the register area of the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns address register name bit symbol r/w description h.rst s.rst b.rst 0x61 ide_config1 7: ide_reset r/w 0: none 1: ide reset 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1:
S1R72801F00A epson 81 address register name bit symbol r/w description h.rst s.rst b.rst 0x63 ide_piodmacyc 7: assert pulse[3] 6: assert pulse[2] r/w ide transfer mode strobe signal assert pulse 5: assert pulse[1] width minimum value 4: assert pulse[0] 0x00 0x00 C 3: negate pulse[3] 2: negate pulse[2] r/w ide transfer mode strobe signal negate pulse 1: negate pulse[1] width minimum value 0: negate pulse[0] ide pio/dma cycle register this register sets a transfer mode when transferring data through the ide interface. it is enabled for an access to 0x70 of the ide-cso register. it is common to both pio/dma modes. bit7::4 asset pulse decides the minimum value of the assert period of the strobe signal when transferring data through the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. bit3::0 negate pulse decides the minimum value of the negate period of the strobe signal when transferring data through the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns address register name bit symbol r/w description h.rst s.rst b.rst 0x64 ide_ultradmacyc 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: cycle time[3] 2: cycle time[2] r/w ide ultra dma transfer mode strobe signal 1: cycle time[1] minimum cycle time 0: cycle time[0] ide ultradma cycle register this register sets a transfer mode when transferring data by the ultra-dma through the ide interface. bit7::4 assert pulse decides the minimum value of the assert period of the strobe signal when transferring data through the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. bit3::0 cycle pulse decides the minimum cycle time of the strobe signal when transferring ultra-dma data through the ide interface. it is a value [assert pulse + 2] times the internal operation clock (50mhz) cycle. example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns
S1R72801F00A 82 epson ide bus status read register this register indicates the status of the signal of the ide interface. bit7 dmarq indicates the state of the hdmarq signal by positive logic. (the status of the dmarq_level bit of the config0 is reflected.) bit6 dmack indicates the state of the xhdmack signal by positive logic. bit5 intrq indicates the state of the hintrq signal by positive logic. bit4 iordy indicates the state of the hiordy signal by positive logic. bit3::2 reserved bit1 diag indicates the state of the xhpdiag signal by positive logic. bit0 dasp indicates the state of the xhdasp signal by positive logic. address register name bit symbol r/w description h.rst s.rst b.rst 0x66 ide_busstat 7: dmarq 6: dmack 5: intrq 4: iordy r indicate ide i/f signals state 0x00 0x00 C 3: 2: 1: diag 0: dasp address register name bit symbol r/w description h.rst s.rst b.rst 0x65 ide_dmactl 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: crc_clear w 0: none 1: crc clear 0x00 0x00 C 3: fifo_clear w 0: none 1: fifo clear 2: ide_abort w 0: none 1: ide transfer abort 1: ide_direction r/w 0: sram C> ide 1: ide C> sram 0: dmastart w 0: none 1: ide dma start ide dma control register this register makes control when transferring data through the ide interface. bit7..5 reserved bit4 crc_clear initializes the internal crc calculation circuit. at start-up of the dma, even the internal circuits are initialized . writing 1 to this bit clears the ide_crc0 and ide_crc1 registers. bit3 fifo_clear clears the fifo for ide data transfer. writing 1 to this bit clears the fifo. bit2 ide_abort use this bit to abort dma data transfer in execution through the ide interface. writing 1 to this bit aborts the dma transfer. bit1 ide_direction specifies a data flow direction for dma data transfer in accordance with the ide. ide_direction:1 ide -> sram (buffer) ide_direction:1 ide <- sram (buffer) bit0 dmastart setting this bit to 1 starts dma transfer between the buffer and the ide interface.
S1R72801F00A epson 83 ide dma status register this register indicates the status of the dma of the ide interface. bit7::2 reserved bit1 dmapause indicates whether the dma mode in execution is in pause status or not. it is enabled when the dmarun bit is 1. dmapause:1 dma is in pause. dmapause:0 dma is in execution. bit0 dmarun indicates whether the dma mode in execution is in execution or not. it is enabled when the dmarun bit is 1. dmapause:1 dma is in execution. dmapause:0 dma is not in execution. address register name bit symbol r/w description h.rst s.rst b.rst 0x67 ide_dmastat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 C 3: 0: 1: 2: 0: 1: 1: dmapause r 0: ide dma not pause 1: ide dma pause 0: dmarun w 0: not dma 1: ide dma running
S1R72801F00A 84 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x68 ide_bytecount0 7: bytecount[31] 6: bytecount[30] 5: bytecount[29] 4: bytecount[28] 0x00 0x00 C 3: bytecount[27] 2: bytecount[26] 1: bytecount[25] 0: bytecount[24] 0x69 ide_bytecount1 7: bytecount[23] 6: bytecount[22] 5: bytecount[21] 4: bytecount[20] 0x00 0x00 C 3: bytecount[19] 2: bytecount[18] r/w ide data transfer byte count register 1: bytecount[17] read: indicate remain byte count 0: bytecount[16] write: set total transfer byte count 0x6a ide_bytecount2 7: bytecount[15] 6: bytecount[14] 5: bytecount[13] 4: bytecount[12] 0x00 0x00 C 3: bytecount[11] 2: bytecount[10] 1: bytecount[9] 0: bytecount[8] 0x6b ide_bytecount3 7: bytecount[7] 6: bytecount[6] 5: bytecount[5] 4: bytecount[4] 0x00 0x00 C 3: bytecount[3] 2: bytecount[2] 1: bytecount[1] 0: bytecount[0] ide byte count set register this register sets a total data length in dma transfer in the unit of byte. by setting each register of ide_bytecount0 to 3, setting up to max. 0xffffffff is possible. if you set an odd byte to this register or the oddstart bit of the config0 register when using the data port of the ide bus based on word size, 1 byte is short at the first or last transfer. it is automatically padded by the ic (data is undefined).
S1R72801F00A epson 85 address register name bit symbol r/w description h.rst s.rst b.rst 0x6c ide_crc0 7: crc[15] 6: crc[14] 5: crc[13] 4: crc[12] 0x00 0x00 C 3: crc[11] 2: crc[10] 1: crc[9] 0: crc[8] r ide crc data register 0x6d ide_crc1 7: crc[7] 6: crc[6] 5: crc[5] 4: crc[4] 0x00 0x00 C 3: crc[3] 2: crc[2] 1: crc[1] 0: crc[0] crc read register this register indicates crc calculation results when transferring data by the ultra-dma through the ide interface.
S1R72801F00A 86 epson ide command block register this register is a command block register that is the i/o port of the ide interface. the transfer mode of the data register is pio mode-fixed, having access based on conditions set on the ide_piodmacyc register. since the setting at the bus8/swap bit of the config register is reflected, 16-bit access is possible by always accessing the data register twice if it is 16 bits wide. during dma transfer, access to the data register is disabled. if you access the 0x71-0x77 in the dma mode or when the interlock bit is not on, the hdmarq is negated once and cpu access is done. when the interlock bit is on or at the time of ultradma, the xhdmack is negated at the time of hdmaqr off or on completion of transfer. note that, for this reason, the cpu access is put in wait state. address register name bit symbol r/w description h.rst s.rst b.rst 0x70 ide_cs00 7: 6: command block register 5: 4: r/w data register 0x00 0x00 C 3: 2: 1: 0: 0x71 ide_cs01 7: 6: command block register 5: 4: r/w read : error register 0x00 0x00 C 3: write: features register 2: ultradmamode 1: 0: 0x72 ide_cs02 7: 6: command block register 5: 4: r/w sector count register 0x00 0x00 C 3: 2: 1: 0: 0x73 ide_cs03 7: 6: command block register 5: 4: r/w sector number register or 0x00 0x00 C 3: logical block address(lba) bit 0 C 7 2: 1: 0: 0x74 ide_cs04 7: 6: command block register 5: 4: r/w cylinder low register or 0x00 0x00 C 3: logical block address(lba) bit 8 C 15 2: 1: 0: 0x75 ide_cs05 7: 6: command block register 5: 4: r/w cylinder high register or 0x00 0x00 C 3: logical block address(lba) bit 16 C 23 2: 1: 0: 0x76 ide_cs06 7: 6: command block register 5: 4: r/w device/head register 0x00 0x00 0x00 C 3: logical block address(lba) bit 24 C 27 2: 1: 0: 0x77 ide_cs07 7: 6: command block register 5: 4: r/w read : status register 0x00 0x00 0x00 C 3: write: command register 2: 1: 0:
S1R72801F00A epson 87 ide command control register this register is a command block register that is the i/o port of the ide interface. address register name bit symbol r/w description h.rst s.rst b.rst 0x78 ide_cs10 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x79 ide_cs11 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7a ide_cs12 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7b ide_cs13 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7c ide_cs14 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7d ide_cs15 7: 6: control block register 5: 4: r/w read : data bus hi C impedance 0x00 0x00 C 3: write: not used 2: 1: 0: 0x7e ide_cs16 7: 6: control block register 5: 4: r/w read : alternate status 0x00 0x00 C 3: write: device control 2: 1: 0: 0x7f ide_cs17 7: 6: control block register 5: 4: r/w read : (obsolete) 0x00 0x00 C 3: write: not used 2: 1: 0:
S1R72801F00A 88 epson 8.2 flash rom control register address register name bit symbol r/w description h.rst s.rst b.rst 0x200000 flashctl 7: flashctlenb r/w 0: flash control disable 1: flash control enable 6: 0: 1: 5: 0: 1: 4: erase w 0: none 1: erase execute 0x00 0x00 C 3: flashstat r 0: write/erase complete 1: write/erase run 2: flashchipers r/w 0: chip all erase disable 1: chip all erase enable 1: flashscters r/w 0: sector erase disable 1: sector erase enable 0: flashwrenb r/w 0: flash data write disable 1: flash data write enable flash control register this register controls the erase and write of the built-in flash. bit7 flashctlenb enables flash control. setting this bit to 1 enables the lower order 5 bits of this register. setting 0 disables having access to the built-in flash. bit6 reserved bit5 reserved bit4 erase setting this bit to 1 starts to erase the built-in flash. this bit is read-only. if you read it, it always indicates zero. setting this bit to 1 at the time of flashscters=1, the flash address is updated after erasing one sector. bit3 flashstat indicates the operation of write/erase. 1: in execution 0: processing finishes. bit2 flashchipers use this bit to erase all the built-in flash. 1: all erase is enabled.. 0: all erase is disabled. bit1 flashscters use this bit to erase the built-in flash in the unit of sector. it enables the erase of the sector address set on the flash address. 1: sector erase is enabled.. 0: sector erase is disabled. bit1 flashwrenb enables data write into the built-in flash. 1: data write is enabled.. 0: data write is disabled. sequence to set a default value on flashctlcnt_reg turn on one of bit0, bit1 or bit2 to select a desired operation. next, turn on bit7. sequence to set a value on flashctlcnt_reg turn on bit7 and one of bit0, bit1 and bit2. next, set a value on the flashctlcnt_reg.
S1R72801F00A epson 89 address register name bit symbol r/w description h.rst s.rst b.rst 0x200001 flashctlcnt_h 7: 0: 1: 6: 0: 1: 5: flashctlcnt[21] 4: flashctlcnt[20] if(flashchipers==1 && flashscters==0 && 0x00 0x00 C 3: flashctlcnt[19] flashwrenb==0){ 2: flashctlcnt[18] r/w enable; 1: flashctlcnt[17] default value = 0x3fffff; 0: flashctlcnt[16] } 0x200002 flashctlcnt_m 7: flashctlcnt[15] erase if(flashchipers==0 && flashscters==1 && 6: flashctlcnt[14] flashwrenb==0){ 5: flashctlcnt[13] r/w enable; 4: flashctlcnt[12] r/w default value = 0x0fffff; 0x00 0x00 C 3: flashctlcnt[11] } 2: flashctlcnt[10] erase if(flashchipers==0 && flashscters==0 && 1: flashctlcnt[9] flashwrenb==1){ 0: flashctlcnt[8] r/w enable; 0x200003 flashctlcnt_l 7: flashctlcnt[7] default value = 0x000190; 6: flashctlcnt[6] } else { 5: flashctlcnt[5] read is alway zero; 4: flashctlcnt[4] write is ignore; 0x00 0x00 C 3: flashctlcnt[3] } 2: flashctlcnt[2] 1: flashctlcnt[1] 0: flashctlcnt[0] flash control count register this register is enabled when the flashchipers bit, flashscters bit or flashwrenb bit of the flashctl register is set alone. it is disabled when two or more bits are set. when setting them in the unit of byte, conform to the order of flashctlcnt_h (higher order byte), flashctlcnt_m, and flashctlcnt_l (lower order byte). on completion of writing to the lower order byte, setting of this register is enabled. pulse width (default value) flashchipers: 40ns x 0x3fffff = 167.8ms flashscters: 40ns x 0x0fffff = 41.9ms flashwrenb: 40ns x 0x000190 = 16.0 m s
S1R72801F00A 90 epson address register name bit symbol r/w description h.rst s.rst b.rst 0x200004 flashadrs_h 7: flash address[15] 6: flash address[14] 5: flash address[13] 4: flash address[12] write: flash write/erase sector address set 0x00 0x00 C 3: flash address[11] read: current flash sector address 2: flash address[10] 1: flash address[9] when all of sector are erased, this address is ignored. 0: flash address[8] r/w when data register's low byte is accessed, 0x200005 flashadrs_m 7: flash address[7] this register is updated. 6: flash address[6] 5: flash address[5] 4: flash address[4] 0x00 0x00 C 3: flash address[3] 2: flash address[2] 1: flash address[1] 0: reserved(always zero) flash address register this register specifies a write/erase address of the built-in flash. in the built-in flash all erase mode, the setting of this register is ignored. during writing operation, writing to the lower order byte of the flash data register increments the address of this register. address register name bit symbol r/w description h.rst s.rst b.rst 0x200006 flashdata_h 7: flash address[15] 6: flash address[14] 5: flash address[13] 4: flash address[12] write: flash write data set 0x00 0x00 C 3: flash address[11] read: flash address's word data is read. 2: flash address[10] 1: flash address[9] when operation is write, it shall be set from high byte. 0: flash address[8] r/w because when data register's low byte is accessed, 0x200007 flashdata_l 7: flash address[7] flash address is updated. 6: flash address[6] 5: flash address[5] 4: flash address[4] 0x00 0x00 C 3: flash address[3] 2: flash address[2] 1: flash address[1] 0: flash address[0] flash write data register this register specifies write data of the built-in flash. when setting it in the unit of byte, conform to the order of higher order byte - lower order byte. if you reverse the order, data cannot be correctly written. writing to the lower order byte updates the flash address register to the next write address.
S1R72801F00A epson 91 item symbol rating unit supply voltage hv dd C0.3 to 7.0 v lv dd C0.3 to 4.0 v input voltage hv in C0.3 to hv dd + 0.5 v lv in C0.3 to lv dd + 0.5 v output voltage hv out C0.3 to hv dd + 0.5 v lv out C0.3 to lv dd + 0.5 v output current/pin i out C30 ma storage temperature t stg C65 to 150 c 9. electrical characteristics 9.1 absolute maximum ratings 9.2 recommended operating condition item symbol min. typ. max. unit supply voltage hv dd 4.5 5 5.5 v lv dd 3 3.3 3.6 v input voltage hv in v ss Chv dd v lv in v ss Clv dd v operating temperature topr1 0 C 70 c operating temperature when topr2 0 C 70 c writing to flash rom
S1R72801F00A 92 epson 9.3 dc characteristics (according to recommended operating condition) (1) (hv dd = 5.0v 0.5v, lv dd = 3.3v 0.3v, ta = 0 to 70 c) item symbol condition min. typ. max. unit power supply current power supply current i dd hv dd =5.5v C C 150 ma lv dd =3.6v static current (static current between hv dd to v ss ) power supply current i ddsh v in =hv dd or lv dd CC45 m a or v ss hv dd =5.5v lv dd =3.6v static current (static current between lv dd to v ss ) power supply current i ddsl v in =hv dd or lv dd CC90 m a or v ss hv dd =5.5v lv dd =3.6v input leak input leak current i l hv dd =5.5v C1 C 1 m a lv dd =3.6v hv ih =hv dd lv ih =lv dd v il =v ss input characteristics (cmos) high level input voltage v ih1h hv dd =5.5v 3.5 C C v low level input voltage v il1h hv dd =4.5v C C 1 v input characteristics (ttl) high level input voltage v ih2h hv dd =5.5v 2 C C v low level input voltage v il2h hv dd =4.5v C C 0.8 v input characteristics (cmos) high level input voltage v ih1l hv dd =3.6v 2 C C v low level input voltage v il1l hv dd =3.0v C C 0.8 v schmitt input characteristics (ttl) high level trigger voltage v t2+ hv dd =5.5v 1.2 C 2.4 v lv dd =3.6v low level trigger voltage v t2C hv dd =4.5v 0.6 C 1,8 v lv dd =3.0v hysteresis voltage dv 2 hv dd =4.5v 0.1 C C v lv dd =3.0v
S1R72801F00A epson 93 dc characteristics (according to recommended operating condition) (1) (hv dd = 5.0v 0.5v, lv dd = 3.3v 0.3v, ta = 0 to 70 c) item symbol condition min. typ. max. unit output characteristics pin name: ctl0, ctl1, d0.. d7 off-state leak current i oz hv dd =5.5v C1 C 1 m a lv dd =3.6v hv oh =hv dd lv oh =lv dd v ol =v ss input characteristics (bus hold) pin name: linkon, sclk, ctl0, ctl1, d0..d7, t18 low level hold current i bhl lv dd =3.0v C C 0.3 ma v bhl =0.4v high level hold current i bhh lv dd =3.0v C0.3 C C ma v bhh =2.6v output characteristics (bus drive) pin name: linkon, sclk, ctl0, ctl1, d0..d7, t18 low level output current v bhl lv dd =3.6v l vdd C0.4 CCv i bhl =0.9ma high level output current v bhh lv dd =3.6v C C v ss +0.4 v i bhh =C0.9ma
S1R72801F00A 94 epson symbol description unit min. max. t 201 sclk frequency 49.152mhz 100ppm t 202 sclk duty cycle % 45 55 t 203 sclk start ? hclk start delay time ns 5 15 t 204 hclk frequency mhz 20 24.576 t 205 hclk duty cycle % 40 60 9.4 ac characteristics 9.4.1 clock timing 9.4.1.1 sclk timing 9.4.1.2 hclk timing t 201 sclk hclk t 202 t 204 t 205 t 205 t 203 t 202
S1R72801F00A epson 95 symbol description unit min. max. t 214 sclk rising edge ? c, ctl ns 6 set-up time t 215 sclk rising edge ? c, ctl ns 0 hold time symbol description unit min. max. t 211 sclk rising edge ? c, ctl, ns 1 10 lreq delay time (hi-z ? output starts.) t 212 sclk rising edge ? c, ctl, ns 1 10 lreq delay time (outputting) t 213 sclk rising edge ? c, ctl, ns 1 10 lreq delay time (when output ends.) 9.4.2 phy-link interface timing 9.4.2.1 output timing 9.4.2.2 input timing t 211 sclk ctl[0:1] d[0:7] lreq t 212 t 213 sclk ctl[0:1] d[0:7] lreq t 212 t 214
S1R72801F00A 96 epson symbol specification min. typ. max. unit t 321 xhcs0 ? hda C 0 C ns hda output delay time t 322 xhcs0 -? hda C 0 C ns hda hold time t 323 xhcs0 ? xhior 60 C C ns xhior set-up time t 324 xhior ? xhior - C idepio C ns xhior assert pulse time (ap+2) 20 t 325 xhior -? xhior C idepio C ns xhior negate pulse time (np+2) 20 t 326 xhior -? xhcs0 - 20 C C ns xhior hold time t 327 hdd ? xhior - 10 C C ns data set-up time t 328 xhior -? hdd 0 C C ns data hold time t 329 hiordy assert ? xhior - C C 40 ns xhdmack set-up time 9.4.3 ide interface timing 9.4.3.1 pio read t 321 t 324 t 323 t 327 t 328 t 325 t 326 t 329 t 322 hdcso(0) hda<2:0>(0) xhior(0) hdd<15:0>(0) xhiordy(1) direction of data transfer port ? s1r72801 ? host
S1R72801F00A epson 97 symbol specification min. typ. max. unit t 331 xhcs0 ? hda hda output delay time C 0 C ns t 332 xhcs0 -? hda hda hold time C 0 C ns t 333 xhcs0 ? xhiow xhiow set-up time 60 C C ns t 334 xhiow ? xhiow - idepio xhiow assert pulse width C (ap+2) 20 Cns t 335 xhiow -? xhiow idepio xhiow negate pulse width C (np+2) 20 Cns t 336 xhiow -? xhcs0 - xhiow hold time 20 C C ns t 337 xhiow ? hdd data output delay time 0 C 20 ns t 338 xhiow -? hdd data bus negate time 40 C 60 ns t 339 hiordy assert ? xhiow - xhdmack set-up time C C 40 ns 9.4.3.2 pio write t 331 t 334 t 333 t 337 t 338 t 335 t 336 t 339 t 332 hdcso(0) hda<2:0>(0) xhiow(0) hdd<15:0>(0) xhiordy(1) direction of data transfer port ? s1r72801 ? host
S1R72801F00A 98 epson symbol specification min. typ. max. unit t 341 xhcs0,1 -? xhdmack address set-up time 60 C C ns t 342 xhior -? xhcs0,1 address hold time 25 C C ns t 343 hdmarq -? xhdmack xhdmack response time 0 C C ns t 344 xhior ? hdmarq negate hdmarq hold time 0 C C ns t 345 xhdmack ? xhior xhior set-up time 0 C C ns t 346 xhior ? xhior - C ide C ns xhior assert pulse width (ap+2) 20 t 347 xhior -? xhior C ide C ns xhior negate pulse width (ap+2) 20 t 348 xhior -? xhdmack - xhior hold time 20 C C ns t 349 hdd ? xhior - data set-up time 10 C C ns t 34a xhior -? hdd data bus hold time 0 C C ns 9.4.3.3 dma read t 341 t 343 t 345 t 346 t 349 t 34a t 347 t 348 t 344 t 342 direction of data transfer port ? s1r72801 ? host xhcs<1:0>(0) hda<2:0>(0) hdmarq(1) xhdamck(0) xhior(0) hdd<15:0>(1)
S1R72801F00A epson 99 symbol specification min. typ. max. unit t 351 xhcs0,1 -? xhdmack address set-up time 60 C C ns t 352 xhiow -? xhcs0,1 address hold time 20 C C ns t 353 hdmarq -? xhdmack xhdmack response time 0 C C ns t 354 xhiow ? hdmarq negate hdmarq hold time 0 C C ns t 355 xhdmack ? xhiow xhior set-up time 0 C C ns t 356 xhiow ? xhiow - ide xhiow assert pulse width C (ap+2) 20 C ns t 357 xhiow -? xhiow ide xhiow negate pulse width C (ap+2) 20 C ns t 358 xhiow -? xhdmack - xhiow hold time 20 C C ns t 359 xhiow ? hdd data output delay time 0 C 20 ns t 35a xhior -? hdd data bus negate time 20 C 40 ns 9.4.3.4 dma write t 351 t 353 t 355 t 356 t 359 t 35a t 357 t 358 t 354 t 352 direction of data transfer port ? s1r72801 ? host xhcs<1:0>(0) hda<2:0>(0) hdmarq(1) xhdamck(0) xhiow(0) hdd<15:0>(0)
S1R72801F00A 100 epson symbol specification min. typ. max. unit t 361 xhcs0,1 -? xhdmack address set-up time 20 C C ns t 362 xhiow -? xhcs0,1 address hold time 40 C C ns t 363 hdmarq -? xhdmack xhdmack response time 20 C C ns t 364 xhdmack ? xhior,xhiow envelop time 20 C C ns t 365 xhior,xhiow ? hiordy first strobe time 0 C C ns t 366 xhior,xhiow ? hdmarq strobe edge to negation dmarq 30 C C ns t 367 hdmarq ? xhior,xhiow?? limited interlock time 40 C 90 ns t 368 hiordy ? xhior - readyCtoCfinal strobe time 20 C 55 ns t 369 xhior -? xhiow - readyCtoCpause time 170 C C ns t 36a hdd ? hiordy - data set-up time 7 C C ns t 36b hiordy -? hdd data hold time 5 C C ns t 36c hiordy -? hdd(crc) interlock time with minimum 0 C C ns t 36d hdd(crc) ? hdmack - crc data set-up time 75 C 95 ns t 36e hdmack -? hdd(crc) crc data hold time 7 C C ns t 36f hiordy -? hiordy hiordy pulse width 55 C C ns 9.4.3.5 ultra-dma read t 361 t 364 t 368 t 365 t 36b t 36c t 36d t 36e t 36a t 36f t 367 t 362 t 366 t 363 t 369 crc direction of data transfer port ? s1r72801 ? host xhcs<1:0>(0) hda<2:0>(0) hdmarq(1) xhdamck(0) xhiow(0) xhhior(0) hiordy(0) hdd<15:0>(1)
S1R72801F00A epson 101 9.4.3.6 ultra-dma write symbol specification min. typ. max. unit t 371 xhcs0,1 -? xhdmack address set-up time 20 C C ns t 372 xhdmck -? xhcs0,1 address hold time 40 C C ns t 373 hdmarq -? xhdmack xhdmack response time 20 C C ns t 374 xhdmack ? xhiow envelop time 20 C C ns t 375 xhiow ? hiordy limited interlock time 40 C C ns t 376 hiordy ? xhior unlimited interlock time C C C ns t 377 xhior ? hdmarq strobe edge to negation dmarq 30 C C ns t 378 hdmarq ? xhior - limited interlock time 40 C 90 ns t 379 xhior -? hiordy - strobe to dmardy time (cyc+2) 20 C55ns t 37a xhior ? xhiow - strobe edge to nagation stop 50 C C ns t 37b hdmack hdd data output delay time C C C ns t 37c xhior -? hdd data negate time 20 C C ns t 37d hiordy -? hdd(crc) interlock time with minimum C C C ns t 37e hdd(crc) ? hdmack - crc data set-up time 75 C 95 ns t 37f hdmack -? hdd(crc) crc data hold time 7 C C ns t 37g hiordy -? hiordy hiordy pulse width C C C ns t 371 t 37c t 37d t 374 t 375 t 376 t 37b t 379 t 37e t 37f t 372 t 377 t 37a t 378 t 373 direction of data transfer port ? s1r72801 ? host xhcs<1:0>(0) hda<2:0>(0) hdmarq(1) xhdamck(0) xhiow(0) xhhior(0) hiordy(1) hdd<15:0>(0) crc
S1R72801F00A 102 epson 9.4.4 cpu interface timing regarding the built-in cpu, refer to the e0c33208/204/202 technical manual. in the built-in cpu core, however, a dma controller and a/d converter are not integrated; this part is different from the description on the dma controller and a/d converter given in technical manual. a low-speed oscillation circuit (osc1) is not available.
S1R72801F00A epson 103 10. examples of external connection for reference purposes 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cr12 0 cr1 0 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr13 cr14 1000pf 1000pf 1000pf 100pf 1000pf 1000pf 1000pf 1000pf 1000pf 1000pf 1000pf 1000pf 1 2 1 2 3 4 +12v gnd gnd +6v r49 r50 r51 r52 5 6 7 8 4 3 2 1 10k 10k 10k 10k cr16 10k r54 1000pf linkon(2d3) 2 3 4 5 6 1 2 3 4 5 6 1 vg tpb* tpb tpa* tpa shell vp 5.1k 1.2k r35 r70 (1%) rm5 56 tsb41lv02 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 c11 c12 0.1u 0.1u 10p 10p 1000p 24.576mhz pvdd rst (h4) x1 c29 c30 c13 ops (h5) agng tpb0 tpb0+ tpa0 tpa0+ tpbias0 agnd r0 r1 av dd tpb1 tpb1+ tpa1 tpa1+ tpbias1 agnd v dd -5v lps pd d7 d6 d5 d4 d3 d2 d1 d0 ctl1 ctl0 cna sysclk lreq pd ld7 ld6 ld5 ld4 ld3 ld2 ld1 ld0 ctrl1 ctrl0 cna sclk lreq r71 r72 r73 r74 0 0 0 0 (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d3) (2d4) (2d4) (2d4) agnd av dd av dd sm se testm dv dd dv dd cps xiso pc2 pc1 pc0 c/lkon dgnd dgnd agng agnd av dd av dd reset filter0 filter1 pllv dd pllgnd pllgnd xi xo dv dd dv dd dgnd dgnd 1 2 3 4 5.1k r37 c9 c27 c25 1u + 0.01u 220p 8 7 6 5 rm6 56 1 2 3 4 5.1k r38 c10 c28 c25 1u + 0.01u 220p 8 7 6 5 cn1 d1 hrw0202a pv dd 1 vp (c6) 2 rst cps 3 r40 390k pv dd pv dd u2 pv dd cn3 con4 12v cr1 ` 16 dmt7281d dmt7281i cr15 1000pf lps (2d3) 0 mounted 1000pf mounted r43 10k 10k r55 10k r56 r57 4.7k r44 pv dd dsw1 swdip-4 1k (f3) (e5) socket vg tpb* tpb tpa* tpa shell vp cn2 socket pattern width and length should be equal shortest pattern (100ppm) bus holder with pull-down pd,linkon,cna,lps power supply connector for 2.5" hdd 0.1u c37 led1 pg dg hv dd tlr124 1k r45 power d3v pv dd r75 r76 r77 r78 0 0 0 0 pg dg r75 r76 r77 r78 0 0 0 0 pg dg c50 c51 c23 0.1u 0.01u 1000p pv dd c32 25 27pin 0.1u c14 1000p c15 1000p pv dd c33 30,31pin 32pin 0.1u c16 1000p c17 1000p pv dd c34 42pin 0.1u c18 1000p c19 1000p pv dd c35 51,52pin 49,50pin 0.1u c20 1000p c21 1000p pv dd c38 61,62pin 63,64pin 0.1u pv dd c31 16pin 17,18pin 0.1u c22 1000p d5v p5v psv cn6 con2 jp1 jump-3 hmdd d3v 1 2 2 2 3 13 c5 c36 v in gnd v out ba033fp jp1 1-2 2-3 current new u8 0.1u 47u 22u c3 22u c2 c4 47u + + 3 1 v in gnd v out ba05fp d2 hrf503a vp f1 smd0302 (g5) d5 hrf503a u7 + + psv
S1R72801F00A 104 epson led3 tly124 cn5 3 0 1 jump-3 jp3 c8 4.7k led3 tlg124 tlg124 led4 1k 1k r46 r47 r42 100p c7 5p 1 1 1 1 1 2 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 a18 a19 a20 a21 a22 a23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 1 2 4 3 1 3 2 2 1 1 nc1 nc2 ft1f-2m nc1 nc2 ft1d-2m 3 sw2 sw3 th th1 1 cp cp1 1 th th2 1 th th5 lreq sclk (1d4) xce10ex (3g4) (1d4) cna (1d4) ctrl0 (1d4) ctrl1 (1d4) ld0 (1d4) ld1 (1d4) ld2 (1d4) ld3 (1d4) ld4 (1d4) ld5 (1d4) ld6 (1d4) ld7 (1d4) pd (1d4) lps (1c4) linkon (1e6) r79 r80 r81 r82 r83 r84 r85 r86 r87 r88 r89 r90 r91 r92 r93 r94 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 v ss n.c bclk hclk v ss icemd xreset xnmi hv dd dsio p10 v ss osc4 osc3 v ss p11 p12 p13 p14 hv dd ea10md2 ea10md1 ea10md0 plls1 plls0 v ss pllc v ss ramtst x2spdx p07 p06 p05 p04 p03 p02 v ss p01 p00 xwait k67 k66 p23 p22 n.c lv dd lv dd n.c ad18 ad19 ad20 ad21 ad22 ad23 flstst xhdasp v ss tvep xhcs1 xhcs0 hda2 hda0 xhpdiag hda1 hintrq xhdmack hv dd hiordy xhior xhiow hdmarq hdd15 hdd0 hdd14 v ss hdd1 hdd13 hdd2 hdd12 hdd3 hdd11 hdd4 hv dd hdd10 hdd5 hdd9 hdd8 hdd8 hdd7 xhrst n.c v ss S1R72801F00A1 lv dd n.c dt0 dt1 hv dd dt2 dt3 dt4 dt5 dt6 dt7 dt8 v ss dt9 dt10 dt11 dt12 dt13 dt14 dt15 hv dd xwrh xwrl xrd ad0 ad1 ad2 ad3 vss ad4 ad5 ad6 ad7 ad8 ad9 ad10 hv dd ad11 ad12 ad13 ad14 ad15 ad16 ad17 n.c v ss v ss n.c p21 p20 xce10ex xce9 monxwait xce6 hv dd to0 to1 to2 to3 to4 to5 to6 to7 ti8 monxint v ss v ss v ss v ss lreq lv dd sclk v ss cna xiso bhen ctl0 ctl1 d0 d1 d2 lv dd d3 d4 d5 d6 d7 pd lps linkon n.c lv dd reset gnd d07 d08 d06 d09 d05 d10 d04 d11 d03 d12 d02 d13 d01 d14 d0 d15 gnd nc dmarq gnd didw gnd didr gnd iordy csel dmack gnd intrq nc da1 pdiag da0 da2 cs0 cs1 dasp gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 xhdasp 33 r79 xhrst (e2) 8 rm1 1 hdd7 (e2) 6 33 1 hdd6 (e2) 5 1 hdd9 (e2) 8 rm2 1 hdd5 (e2) 7 1 hdd10 (e2) 6 33 1 hdd4 (e2) 5 1 hdd11 (e2) 8 rm3 1 hdd3 (e2) 7 1 hdd12 (e2) 6 33 1 hdd2 (e2) 5 1 hdd13 (f2) 8 rm4 1 hdd1 (f2) 7 1 hdd14 (f2) 6 33 1 hdd0 (f2) 5 1 hdd15 (f2) 82 r22 hidmaro (f2) 22 r23 xhow r65 0 r69 0 (f2) 22 r24 xhor (f2) 82 r25 hiordy (f2) 22 r26 xhdmack (f2) 82 r27 hintro (f2) 33 r28 hda1 (f2) 0 r29 xhpdag (f2) 33 r30 hda0 (f2) 33 r31 hda2 (f2) 33 r32 xhcs0 (f2) 33 r33 xhcs1 (f2) (g2) 7 2 hdd8 (e2) xresft (g1) dso (b6) ds1o (b6) xhdasop (c5) (b3) xhcs1 (a3) xhcs0 (a3) hda2 (a3) hda0 (a3) xhpdag (a3) hda1 (a3) hintro (a3) xhdmack (a3) hiordy (a3) xhor (a3) xhow (a3) hdmaro (a3) hdd15 (a4) hddd0 (a4) hdd14 (a4) hdd1 (a4) hdd13 (a4) hdd2 (a4) hdd12 (a4) hdd3 (a4) hdd11 (a4) hdd4 (a4) hdd10 (a4) hdd5 (a4) hdd9 (a4) hdd6 (a4) hdd8 (a4) hdd7 (a4) xhrst (a5) ds11 (b6) ds12 (b6) dpco (b5) do1k (b6) plls1 (c6) plls0 cp cp7 cpcp8 p21 cp cp6 cp cp5 cp cp4 1 cp cp3 1 cp cp2 th th4 1 th th3 (c6) x2spdx (c6) fa10mdp (c6) d3v uv dd uv dd hv dd d3v dsw3 sw dip-2 dsw2 4 5 fa10md2 (f6) 3 6 plls1 (f6) 2 7 plls0 (f6) 1 8 x2spdx r60 r61 r62 r63 10k 10k 10k 10k (f6) xhdasp 510 r48 (g2) sw dip-4 10k 10k r58 r59 lv dd hv dd hv dd hv dd uv dd hv dd jumper jp5 cp cp9 con40 r68 5.6k 1k r64 hv dd uv dd xreset xreset (3f5)(g6) r41 33k ct u5 mb3771pf vsc out gnd rst vsa vsb v cc (3d6) d[0:15] (3f6) a[0:23] 8 7 6 5 1 2 3 4 xwrl (3f4) xrd (3f4) lv dd u1 8 4 1 5 c39 v cc x2 sg8002jc-25m-pcmb gnd oe out 0.1u shortest pattern momentary pattern length is within 5cm not mounted yet toggle bclk on msc monxint gnd wait dsk c52 c40 0.1u 1u c41 0.1u c42 0.1u c43 0.1u c44 0.1u lv dd c45 0.1u c46 0.1u c47 0.1u sw(skhhal) ma739 c24 1000p d4 sw1 1 2 3 4 12 lv dd d3v jumper jp6 12 1 dso dst2 (g6) (f6) dclk (f6) dst1 (f6) dst0 (g6) dpco (f6) r34 icd i/f cn4 con10 33 1 2 3 4 5 6 7 8 9 10
S1R72801F00A epson 105 c48 0.1u hv dd d[0:15] (2h5) (2h2) a[1:18] 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 9 10 13 14 16 15 37 46 27 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d55/a-1 nc nc nc nc nc ry/by v cc gnd gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 ce reset byte oe oe u4 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 29 29 29 29 29 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 v cc v cc v ss v ss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 xub xlb xcs xwe xoe u3 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 d9 d10 d11 d12 d13 d14 d15 38 11 33 12 34 5 4 3 2 1 44 43 42 27 26 25 24 21 20 19 18 40 39 6 17 41 d15 xreset (2g1) mbm29f400tc-70pftn tc551664bft hv dd hv dd c49 0.1u hv dd hv dd xrd (2h4) xwrl (2h4) xce10ex jump-3 jp4 10k r66 10k r67 2 1 3 (2d5) note: the circuit of this sheet is an example of connection when an external rom and sram are connected during the process of system development. this circuit is not required on a system of finished product.
S1R72801F00A 106 epson 11. shape of package 20 0.1 22 0.4 93 138 20 0.1 22 0.4 47 92 index 0.16 46 1 184 139 1.4 0.1 0.1 1.7 max. 1 0.5 0.2 0 10 0.125 0.4 +0.05 ?.03 +0.05 ?.025 plastic qfp20-184 pin
america epson electronics america, inc. headquarters 1960 e. grand avenue el segundo, ca 90245, u.s.a. phone : +1-310-955-5300 fax : +1-310-955-5400 sales offices west 150 river oaks parkway san jose, ca 95134, u.s.a. phone : +1-408-922-0200 fax : +1-408-922-0238 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone : +1-815-455-7630 fax : +1-815-455-7633 northeast 301 edgewater place, suite 120 wakefield, ma 01880, u.s.a. phone : +1-781-246-3600 fax : +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone : +1-877-eea-0020 fax : +1-770-777-2637 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone : +49- (0) 89-14005-0 fax : +49- (0) 89-14005-110 sales office altstadtstrasse 176 51379 leverkusen, germany phone : +49- (0) 2171-5045-0 fax : +49- (0) 2171-5045-10 uk branch office unit 2.4, doncastle house, doncastle road bracknell, berkshire rg12 8pe, england phone : +44- (0) 1344-381700 fax : +44- (0) 1344-381701 french branch office 1 avenue de l atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone : +33- (0) 1-64862350 fax : +33- (0) 1-64862355 barcelona branch office barcelona design center edificio prima sant cugat avda. alcalde barrils num. 64-68 e-08190 sant cugat del valles, spain phone : +34-93-544-2490 fax: +34-93-544-2491 asia epson (china) co., ltd. 28f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone : 64106655 fax : 64107319 shanghai branch 4f, bldg., 27, no. 69, gui jing road caohejing, shanghai, china phone : 21-6485-5552 fax : 21-6485-0775 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone : +852-2585-4600 fax : +852-2827-4346 telex : 65542 epsco hx epson taiwan technology & trading ltd. 10f, no. 287,nanking east road, sec. 3 taipei phone : 02-2717-7360 fax : 02-2712-9164 telex : 24444 epsontb hsinchu office 13f-3, no.295, kuang-fu road, sec. 2 hsinchu 300 phone : 03-573-9900 fax : 03-573-9169 epson singapore pte., ltd. no. 1 temasek avenue, #36-00 millenia tower, singapore 039192 phone : +65-337-7911 fax : +65-334-2716 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone : 02-784-6027 fax : 02-767-3677 seiko epson corporation electronic devices marketing division electronic device marketing department ic marketing & engineering group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5816 fax: +81-(0)42-587-5624 ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5812 fax: +81-(0)42-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5814 fax: +81-(0)42-587-5110 international sales operations `
in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no parts of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export licence from teh ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001, all rights reserved. all other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies.
mf1385 - 04 technical manual S1R72801F00A technical manual ieee1394 controller S1R72801F00A technical manual S1R72801F00A epson electronic devices website electronic devices marketing division http://www.epson.co.jp/device/ first issue december,2000 printed march,2001 in japan h a 4.5mm this manual was made with recycle paper, and printed using soy-based inks.

▲Up To Search▲

Price & Availability of S1R72801F00A

	To Download S1R72801F00A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .